erihsu / INT_FP_MAC

Related projects ⓘ

Alternatives and complementary repositories for INT_FP_MAC

• kuladeepsaireddy / OpenNoc
  ☆26Updated 5 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆129Updated 4 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆63Updated last year
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆67Updated 6 years ago
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆152Updated last month
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆123Updated last week
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆32Updated 2 months ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆39Updated 2 years ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆68Updated 2 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆54Updated 3 months ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆93Updated 4 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆91Updated 4 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆71Updated 5 years ago
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆167Updated last year
• ac-optimus / Convolution-using-systolic-arrays
  ☆60Updated 5 years ago
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆36Updated 5 years ago
• taoyilee / clacc
  Deep Learning Accelerator (Convolution Neural Networks)
  ☆166Updated 6 years ago
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆110Updated 6 years ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆12Updated 3 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆100Updated 10 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆18Updated 3 years ago
• pareddy113 / Design-of-various-multiplier-Array-Booth-Wallace-
  ☆19Updated 10 months ago
• IA-C-Lab-Fudan / Chisel-FFT-generator
  FFT generator using Chisel
  ☆56Updated 3 years ago
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆39Updated 4 years ago
• Parimala6 / Floating-point-MAC-verilog
  32 - bit floating point Multiplier Accumulator Unit (MAC)
  ☆24Updated 3 years ago
• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆86Updated 4 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆48Updated 5 months ago
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆127Updated 5 months ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆68Updated 10 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆68Updated 6 years ago