danshanley / FPULinks
IEEE 754 floating point unit in Verilog
☆148Updated 9 years ago
Alternatives and similar repositories for FPU
Users that are interested in FPU are comparing it to the libraries listed below
Sorting:
- An AXI4 crossbar implementation in SystemVerilog☆177Updated last month
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆92Updated 6 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆217Updated 5 years ago
- Network on Chip Implementation written in SytemVerilog☆192Updated 3 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆136Updated 5 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆179Updated 11 months ago
- Basic RISC-V Test SoC☆153Updated 6 years ago
- Various caches written in Verilog-HDL☆126Updated 10 years ago
- AMBA bus generator including AXI, AHB, and APB☆107Updated 4 years ago
- A Fast, Low-Overhead On-chip Network☆231Updated this week
- Vector processor for RISC-V vector ISA☆129Updated 5 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 10 months ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆132Updated 7 years ago
- AXI4 and AXI4-Lite interface definitions☆96Updated 5 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- Verilog Configurable Cache☆184Updated 2 weeks ago
- AXI DMA 32 / 64 bits☆121Updated 11 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆82Updated 7 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆142Updated 2 weeks ago
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆140Updated 3 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆105Updated 5 years ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆64Updated last year
- An implementation of the CORDIC algorithm in Verilog.☆102Updated 6 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆82Updated 2 years ago
- DDR2 memory controller written in Verilog☆78Updated 13 years ago
- round robin arbiter☆75Updated 11 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆52Updated 8 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆113Updated last year