danshanley / FPULinks
IEEE 754 floating point unit in Verilog
☆145Updated 9 years ago
Alternatives and similar repositories for FPU
Users that are interested in FPU are comparing it to the libraries listed below
Sorting:
- An AXI4 crossbar implementation in SystemVerilog☆170Updated this week
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆133Updated 5 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆90Updated 6 years ago
- Various caches written in Verilog-HDL☆125Updated 10 years ago
- Vector processor for RISC-V vector ISA☆126Updated 4 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆129Updated 7 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆217Updated 5 years ago
- A Fast, Low-Overhead On-chip Network☆221Updated 3 weeks ago
- Network on Chip Implementation written in SytemVerilog☆189Updated 3 years ago
- Basic RISC-V Test SoC☆140Updated 6 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆174Updated 9 months ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆68Updated 8 months ago
- IC implementation of TPU☆128Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆104Updated 4 years ago
- SDRAM controller with AXI4 interface☆96Updated 6 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆77Updated 2 years ago
- AMBA bus generator including AXI, AHB, and APB☆106Updated 4 years ago
- Verilog Configurable Cache☆181Updated 8 months ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆79Updated 7 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆182Updated 5 years ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆60Updated last year
- A verilog implementation for Network-on-Chip☆76Updated 7 years ago
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- round robin arbiter☆75Updated 11 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆104Updated last year
- An implementation of the CORDIC algorithm in Verilog.☆98Updated 6 years ago
- ☆68Updated 9 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆58Updated 4 years ago
- IC implementation of Systolic Array for TPU☆272Updated 10 months ago