danshanley / FPU

Related projects: ⓘ

• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆112Updated 3 months ago
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆109Updated 4 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆79Updated 3 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆65Updated 5 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆104Updated 3 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆75Updated 5 years ago
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆137Updated 6 months ago
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆111Updated 9 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆62Updated last year
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆82Updated 3 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆102Updated 5 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆196Updated 4 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆66Updated 6 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆151Updated 2 years ago
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆72Updated 12 years ago
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆100Updated 6 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆82Updated 3 years ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆66Updated 10 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆136Updated last year
• MorrisMA / Booth_Multipliers
  Parameterized Booth Multiplier in Verilog 2001
  ☆46Updated last year
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆95Updated 10 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆165Updated 3 weeks ago
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆31Updated 4 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆81Updated 4 months ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆87Updated 3 years ago
• taneroksuz / fpu
  IEEE 754 floating point library in system-verilog and vhdl
  ☆53Updated 3 months ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆106Updated 3 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆126Updated 2 weeks ago
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆90Updated last year
• zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial
  Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …
  ☆117Updated 2 years ago