IEEE 754 floating point unit in Verilog
☆154May 20, 2016Updated 10 years ago
Alternatives and similar repositories for FPU
Users that are interested in FPU are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- synthesiseable ieee 754 floating point library in verilog☆763Mar 13, 2023Updated 3 years ago
- For CPU experiment☆14Feb 23, 2021Updated 5 years ago
- Basic floating-point components for RISC-V processors☆12Aug 13, 2017Updated 9 years ago
- double_fpu_verilog☆22Jul 17, 2014Updated 12 years ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆77Aug 10, 2024Updated 2 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Basic floating-point components for RISC-V processors☆69Dec 4, 2019Updated 6 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆84Aug 3, 2023Updated 3 years ago
- Mathematical Functions in Verilog☆101Mar 7, 2021Updated 5 years ago
- This repo contains source files and code for a synthesizable RISC-V processor with support for custom instructions in a co-processor.☆12Aug 19, 2018Updated 8 years ago
- zero-riscy CPU Core☆19Jun 10, 2018Updated 8 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆181May 10, 2025Updated last year
- Traces for SVA - SystemVerilog Assertions; Will use Go2UVM package to write traces and use uvm_report_mock to predict errors☆12Sep 2, 2016Updated 10 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆85Jul 18, 2026Updated 3 months ago
- ☆10Mar 11, 2017Updated 9 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆62Feb 18, 2019Updated 7 years ago
- Some beginner projects using verilog HDL, along with some documentation on basic syntax☆14Jun 13, 2021Updated 5 years ago
- ASIC Design of the openSPARC Floating Point Unit☆17Mar 13, 2017Updated 9 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆651Updated this week
- Computer architecture learning environment using FPGAs☆15May 17, 2021Updated 5 years ago
- vector accelerating unit☆37Dec 1, 2020Updated 5 years ago
- ☆11Jan 9, 2021Updated 5 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆104Apr 30, 2019Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL☆15Mar 21, 2024Updated 2 years ago
- An HBM FPGA based SpMV Accelerator☆19Aug 29, 2024Updated 2 years ago
- A Goldschmidt integer divider written in verilog. Similar to Newton-Raphson but the divison step can be pipelined.☆16Apr 25, 2024Updated 2 years ago
- An extention of pytorch for low precision training / inference☆10Aug 28, 2023Updated 3 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆289Nov 6, 2024Updated 2 years ago
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆161Jul 17, 2022Updated 4 years ago
- 32-bit Superscalar RISC-V CPU☆1,329Sep 18, 2021Updated 5 years ago
- Interface Protocol in Verilog☆52Aug 2, 2019Updated 7 years ago
- RTL implementation of Flex-DPE.☆119Feb 22, 2020Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- RTL Verilog library for various DSP modules☆103Feb 17, 2022Updated 4 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Aug 28, 2019Updated 7 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆202Dec 15, 2017Updated 8 years ago
- mor1kx - an OpenRISC 1000 processor IP core☆594Jun 6, 2026Updated 5 months ago
- This repository contains the hardware implementation for Static BFP convolution on FPGA☆10Oct 15, 2019Updated 7 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆16Jul 31, 2024Updated 2 years ago