☆63Feb 18, 2019Updated 7 years ago
Alternatives and similar repositories for fpu
Users that are interested in fpu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- For CPU experiment☆14Feb 23, 2021Updated 5 years ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆27Jun 1, 2026Updated last week
- ASIC Design of the openSPARC Floating Point Unit☆17Mar 13, 2017Updated 9 years ago
- Basic floating-point components for RISC-V processors☆69Dec 4, 2019Updated 6 years ago
- Basic floating-point components for RISC-V processors☆12Aug 13, 2017Updated 8 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆609May 26, 2026Updated 2 weeks ago
- ☆24Oct 8, 2019Updated 6 years ago
- synthesiseable ieee 754 floating point library in verilog☆742Mar 13, 2023Updated 3 years ago
- 6-stage dual-issue in-order superscalar risc-v cpu☆14May 2, 2026Updated last month
- CASLab-GPU simulator in SystemC☆11May 29, 2020Updated 6 years ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆16Nov 12, 2025Updated 6 months ago
- ☆12Feb 15, 2024Updated 2 years ago
- ☆33Jul 9, 2025Updated 11 months ago
- 简单的未优化的SRT除法器☆12Jun 16, 2024Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- double_fpu_verilog☆21Jul 17, 2014Updated 11 years ago
- Advanced Debug Interface☆14Jan 23, 2025Updated last year
- ☆13Jan 14, 2021Updated 5 years ago
- ☆37Dec 10, 2023Updated 2 years ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆70Aug 10, 2024Updated last year
- ☆22Feb 22, 2020Updated 6 years ago
- ☆382Sep 12, 2025Updated 8 months ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- ☆12Feb 16, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,243May 29, 2026Updated last week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆21Jun 2, 2026Updated last week
- Simple single-port AXI memory interface☆50Jun 7, 2024Updated 2 years ago
- ☆30Jun 13, 2021Updated 4 years ago
- A low power platform based on X-HEEP and integrating the ESL-CGRA☆20Nov 12, 2025Updated 6 months ago
- ☆51Jan 9, 2026Updated 5 months ago
- 128KB AXI cache (32-bit in, 256-bit out)☆57May 10, 2021Updated 5 years ago
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 6 months ago
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆20May 20, 2026Updated 3 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Dec 23, 2022Updated 3 years ago
- Open source high performance IEEE-754 floating unit☆96Feb 26, 2024Updated 2 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design☆16May 26, 2026Updated 2 weeks ago
- ☆10Jun 11, 2016Updated 9 years ago
- ☆23Mar 15, 2025Updated last year
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆32Mar 13, 2025Updated last year
- A matrix extension proposal for AI applications under RISC-V architecture☆183Apr 1, 2026Updated 2 months ago