alexforencich / verilog-ethernetLinks
Verilog Ethernet components for FPGA implementation
☆2,820Updated 10 months ago
Alternatives and similar repositories for verilog-ethernet
Users that are interested in verilog-ethernet are comparing it to the libraries listed below
Sorting:
- Verilog PCI express components☆1,500Updated last year
- Verilog AXI components for FPGA implementation☆1,919Updated 10 months ago
- Must-have verilog systemverilog modules☆1,901Updated 5 months ago
- The RIFFA development repository☆859Updated last year
- Verilog AXI stream components for FPGA implementation☆852Updated 10 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,453Updated last month
- Verilog library for ASIC and FPGA designers☆1,382Updated last year
- HDL libraries and projects☆1,824Updated this week
- Various HDL (Verilog) IP Cores☆859Updated 4 years ago
- Open source FPGA-based NIC and platform for in-network compute☆2,169Updated last year
- Verilog I2C interface for FPGA implementation☆669Updated 10 months ago
- The Ultra-Low Power RISC-V Core☆1,693Updated 5 months ago
- Verilog UART☆523Updated 10 months ago
- cocotb: Python-based chip (RTL) verification☆2,210Updated this week
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆606Updated 7 years ago
- 32-bit Superscalar RISC-V CPU☆1,169Updated 4 years ago
- ☆662Updated last week
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,970Updated 3 weeks ago
- Scala based HDL☆1,903Updated this week
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆751Updated 2 years ago
- VeeR EH1 core☆918Updated 2 years ago
- A small, light weight, RISC CPU soft core☆1,496Updated last month
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆885Updated 6 months ago
- SERV - The SErial RISC-V CPU☆1,726Updated this week
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆1,040Updated last month
- Parallel Programming for FPGAs -- An open-source high-level synthesis book☆870Updated this week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,381Updated 3 weeks ago
- Random instruction generator for RISC-V processor verification☆1,236Updated 3 months ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,728Updated 2 weeks ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,878Updated last year