alexforencich / verilog-ethernetLinks
Verilog Ethernet components for FPGA implementation
☆2,701Updated 7 months ago
Alternatives and similar repositories for verilog-ethernet
Users that are interested in verilog-ethernet are comparing it to the libraries listed below
Sorting:
- Verilog PCI express components☆1,432Updated last year
- Verilog AXI components for FPGA implementation☆1,816Updated 7 months ago
- Must-have verilog systemverilog modules☆1,843Updated last month
- The RIFFA development repository☆849Updated last year
- Verilog AXI stream components for FPGA implementation☆830Updated 7 months ago
- cocotb: Python-based chip (RTL) verification☆2,095Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,377Updated this week
- Verilog library for ASIC and FPGA designers☆1,339Updated last year
- HDL libraries and projects☆1,744Updated this week
- Various HDL (Verilog) IP Cores☆835Updated 4 years ago
- Open source FPGA-based NIC and platform for in-network compute☆2,015Updated last year
- Verilog I2C interface for FPGA implementation☆644Updated 7 months ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆594Updated 7 years ago
- Verilog UART☆506Updated 7 months ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,881Updated 2 months ago
- The Ultra-Low Power RISC-V Core☆1,610Updated last month
- Scala based HDL☆1,852Updated this week
- 32-bit Superscalar RISC-V CPU☆1,098Updated 4 years ago
- A small, light weight, RISC CPU soft core☆1,466Updated last month
- RISC-V CPU Core (RV32IM)☆1,538Updated 4 years ago
- ☆636Updated 2 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,121Updated 4 months ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,632Updated last week
- SERV - The SErial RISC-V CPU☆1,645Updated 3 months ago
- Random instruction generator for RISC-V processor verification☆1,171Updated 3 months ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,692Updated last year
- Package manager and build abstraction tool for FPGA/ASIC development☆1,342Updated 2 weeks ago
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆693Updated 2 years ago
- Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)☆861Updated 2 months ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,639Updated 3 weeks ago