alexforencich / verilog-ethernet

Related projects ⓘ

Alternatives and complementary repositories for verilog-ethernet

• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,140Updated 6 months ago
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,518Updated 11 months ago
• pConst / basic_verilog
  Must-have verilog systemverilog modules
  ☆1,656Updated 2 weeks ago
• KastnerRG / riffa
  The RIFFA development repository
  ☆777Updated 5 months ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆745Updated 3 months ago
• analogdevicesinc / hdl
  HDL libraries and projects
  ☆1,529Updated this week
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,193Updated 6 months ago
• cocotb / cocotb
  cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
  ☆1,814Updated this week
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,113Updated this week
• seldridge / verilog
  Repository for basic (and not so basic) Verilog blocks with high re-use potential
  ☆550Updated 6 years ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆710Updated 3 years ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆547Updated 4 months ago
• alexforencich / verilog-uart
  Verilog UART
  ☆424Updated last year
• corundum / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆1,716Updated 4 months ago
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,514Updated last week
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,155Updated 4 months ago
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,284Updated last month
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆865Updated 3 years ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,206Updated 2 weeks ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,305Updated last month
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆822Updated last year
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆838Updated this week
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,274Updated 3 years ago
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆850Updated 2 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆490Updated 10 months ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆841Updated 3 years ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,026Updated 2 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆966Updated 4 months ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆624Updated this week
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆866Updated this week