alexforencich / verilog-ethernet

Related projects ⓘ

Alternatives and complementary repositories for verilog-ethernet

• alexforencich / verilog-pcie
  Verilog PCI express components
  ☆1,132Updated 6 months ago
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,499Updated 11 months ago
• KastnerRG / riffa
  The RIFFA development repository
  ☆774Updated 4 months ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆738Updated 3 months ago
• pConst / basic_verilog
  Must-have verilog systemverilog modules
  ☆1,649Updated this week
• corundum / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆1,703Updated 4 months ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,183Updated 6 months ago
• analogdevicesinc / hdl
  HDL libraries and projects
  ☆1,523Updated this week
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,095Updated this week
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆707Updated 3 years ago
• cocotb / cocotb
  cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
  ☆1,802Updated this week
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆543Updated 3 months ago
• seldridge / verilog
  Repository for basic (and not so basic) Verilog blocks with high re-use potential
  ☆549Updated 6 years ago
• alexforencich / verilog-uart
  Verilog UART
  ☆418Updated last year
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,199Updated this week
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆863Updated 3 years ago
• fpgasystems / fpga-network-stack
  Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
  ☆753Updated 6 months ago
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,268Updated last month
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,132Updated 4 months ago
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,663Updated this week
• Digilent / vivado-library
  ☆572Updated 4 months ago
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆845Updated this week
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,371Updated last month
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆831Updated this week
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,213Updated this week
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,299Updated 3 weeks ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆959Updated 3 months ago
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,501Updated 2 weeks ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆818Updated last year
• WangXuan95 / Xilinx-FPGA-PCIe-XDMA-Tutorial
  Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
  ☆457Updated last year