Alternatives and similar repositories for fft

Users that are interested in fft are comparing it to the libraries listed below

• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆41Updated 5 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 4 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆56Updated this week
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆37Updated 3 weeks ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆62Updated last year
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆37Updated 2 years ago
• chick / visualizer
  Provides dot visualizations of chisel/firrtl circuites
  ☆12Updated 6 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆61Updated last year
• pulp-platform / axi_llc
  ☆29Updated last month
• sequencer / arithmetic
  ☆33Updated 2 months ago
• Ghonimo / Formal-Verification-With-VC-Formal--Tutorials-and-Examples
  This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…
  ☆28Updated last year
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆83Updated last year
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• hyoukjun / microswitch-noc
  ☆27Updated 5 years ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆76Updated 9 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆63Updated 5 years ago
• ljgibbslf / basic_cache_core
  ☆28Updated 4 years ago
• pulp-platform / cluster_interconnect
  ☆13Updated last week
• embecosm / ri5cy
  The PULP RI5CY core modified for Verilator modeling and as a GDB server.
  ☆23Updated 6 years ago
• vlsi-lab / len5
  LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.
  ☆16Updated last year
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆32Updated 3 years ago
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆32Updated 5 months ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆28Updated 2 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆50Updated last year
• yaozhaosh / chisel-aes
  Chisel implementation of AES
  ☆23Updated 5 years ago
• pulp-platform / quadrilatero
  matrix-coprocessor for RISC-V
  ☆16Updated last month
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆61Updated 6 months ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆20Updated 3 years ago
• oprecomp / DDR4_controller
  ☆58Updated 4 years ago
• IBM / esp-chisel-accelerators
  Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)
  ☆24Updated 5 years ago