Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.
☆56Nov 24, 2019Updated 6 years ago
Alternatives and similar repositories for firechip
Users that are interested in firechip are comparing it to the libraries listed below
Sorting:
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Nov 22, 2019Updated 6 years ago
- Fluid Pipelines☆11May 4, 2018Updated 7 years ago
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆87Oct 9, 2025Updated 5 months ago
- ☆22Oct 24, 2020Updated 5 years ago
- Comment on the rocket-chip source code☆179Oct 19, 2018Updated 7 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆153Jan 8, 2026Updated 2 months ago
- RocketChip RoCC Accelerator template (Risc-V, Chisel )(加速器开发项目框架)☆15Sep 5, 2019Updated 6 years ago
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 7 years ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,001Mar 9, 2026Updated last week
- A vector processor implemented in Chisel☆21Aug 3, 2014Updated 11 years ago
- DEPRECATED. Please use Chipyard (https://github.com/ucb-bar/chipyard) to build BOOM☆37Oct 23, 2019Updated 6 years ago
- Wrapper for Rocket-Chip on FPGAs☆136Oct 5, 2022Updated 3 years ago
- ☆13Jan 20, 2021Updated 5 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆314Mar 6, 2026Updated 2 weeks ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆222Jan 23, 2020Updated 6 years ago
- RISC-V port to Parallella Board☆13Aug 22, 2016Updated 9 years ago
- Chisel Learning Journey☆109Apr 5, 2023Updated 2 years ago
- Network components (NIC, Switch) for FireBox☆19Oct 27, 2024Updated last year
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Oct 5, 2017Updated 8 years ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆222Dec 23, 2025Updated 2 months ago
- CoreIR Symbolic Analyzer☆75Oct 27, 2020Updated 5 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- ☆110Oct 19, 2018Updated 7 years ago
- ASIC Design of the openSPARC Floating Point Unit☆15Mar 13, 2017Updated 9 years ago
- ☆88Updated this week
- ☆33Jul 28, 2020Updated 5 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Feb 24, 2023Updated 3 years ago
- Examples from the Openlane repository, adapted as Fusesoc cores☆12May 18, 2021Updated 4 years ago
- A cross platform, formally verified, open source, hyperRAM controller with simulator☆14Feb 22, 2019Updated 7 years ago
- Public repository of the UCSC CMPE220 class project☆10Oct 8, 2017Updated 8 years ago
- BSC Development Workstation (BDW)☆32Feb 16, 2026Updated last month
- A Library of Chisel3 Tools for Digital Signal Processing☆245Apr 29, 2024Updated last year
- Python module containing verilog files for rocket cpu (for use with LiteX).☆14Jan 16, 2026Updated 2 months ago
- AWS Shell for FireSim☆13Nov 13, 2024Updated last year
- Chisel/Firrtl execution engine☆155Aug 21, 2024Updated last year
- Fast TLB simulator for RISC-V systems☆16May 16, 2019Updated 6 years ago
- NoC based MPSoC☆11Jul 17, 2014Updated 11 years ago
- educational microarchitectures for risc-v isa☆740Sep 1, 2025Updated 6 months ago
- A Style Guide for the Chisel Hardware Construction Language☆109Jul 16, 2021Updated 4 years ago