Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.
☆56Nov 24, 2019Updated 6 years ago
Alternatives and similar repositories for firechip
Users that are interested in firechip are comparing it to the libraries listed below
Sorting:
- Fluid Pipelines☆11May 4, 2018Updated 7 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Nov 22, 2019Updated 6 years ago
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆87Oct 9, 2025Updated 4 months ago
- ☆22Oct 24, 2020Updated 5 years ago
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 6 years ago
- Comment on the rocket-chip source code☆179Oct 19, 2018Updated 7 years ago
- RISC-V port to Parallella Board☆13Aug 22, 2016Updated 9 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆153Jan 8, 2026Updated last month
- RocketChip RoCC Accelerator template (Risc-V, Chisel )(加速器开发项目框架)☆15Sep 5, 2019Updated 6 years ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆997Feb 20, 2026Updated last week
- A vector processor implemented in Chisel☆21Aug 3, 2014Updated 11 years ago
- CoreIR Symbolic Analyzer☆74Oct 27, 2020Updated 5 years ago
- Chisel Learning Journey☆108Apr 5, 2023Updated 2 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆222Jan 23, 2020Updated 6 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆313Feb 20, 2026Updated last week
- DEPRECATED. Please use Chipyard (https://github.com/ucb-bar/chipyard) to build BOOM☆37Oct 23, 2019Updated 6 years ago
- ☆87Jan 30, 2026Updated last month
- Public repository of the UCSC CMPE220 class project☆10Oct 8, 2017Updated 8 years ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆221Dec 23, 2025Updated 2 months ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Oct 5, 2017Updated 8 years ago
- A collection of RFSoC introductory notebooks for PYNQ.☆26Oct 29, 2021Updated 4 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆244Apr 29, 2024Updated last year
- Examples from the Openlane repository, adapted as Fusesoc cores☆12May 18, 2021Updated 4 years ago
- Wrapper for Rocket-Chip on FPGAs☆137Oct 5, 2022Updated 3 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- AWS Shell for FireSim☆13Nov 13, 2024Updated last year
- A cross platform, formally verified, open source, hyperRAM controller with simulator☆14Feb 22, 2019Updated 7 years ago
- NASTI slave compliant DDRx memory controller.☆11Aug 5, 2016Updated 9 years ago
- Chisel/Firrtl execution engine☆155Aug 21, 2024Updated last year
- BSC Development Workstation (BDW)☆32Feb 16, 2026Updated last week
- The RTL source for AnyCore RISC-V☆33Mar 18, 2022Updated 3 years ago
- ☆33Jul 28, 2020Updated 5 years ago
- educational microarchitectures for risc-v isa☆740Sep 1, 2025Updated 5 months ago
- ASIC Design of the openSPARC Floating Point Unit☆15Mar 13, 2017Updated 8 years ago
- NoC based MPSoC☆11Jul 17, 2014Updated 11 years ago
- Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program☆30Sep 17, 2025Updated 5 months ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆91Jul 29, 2019Updated 6 years ago
- RISC-V Frontend Server☆64Mar 31, 2019Updated 6 years ago
- Python Jupyter Notebooks and FPGA designs showcasing what myHDL can do over traditional Verilog or VHDL☆36Sep 24, 2018Updated 7 years ago