firesim / firechipLinks
Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.
☆56Updated 6 years ago
Alternatives and similar repositories for firechip
Users that are interested in firechip are comparing it to the libraries listed below
Sorting:
- OmniXtend cache coherence protocol☆82Updated 6 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆152Updated last month
- ☆51Updated 3 months ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 6 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆181Updated 7 months ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- Original RISC-V 1.0 implementation. Not supported.☆42Updated 7 years ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 6 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆87Updated 4 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆168Updated 5 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆67Updated 3 years ago
- ☆87Updated last week
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- Lipsi: Probably the Smallest Processor in the World☆89Updated last year
- An implementation of RISC-V☆46Updated 3 weeks ago
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆87Updated 2 months ago
- pulp_soc is the core building component of PULP based SoCs☆81Updated 9 months ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- A time-predictable processor for mixed-criticality systems☆60Updated last year
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Updated last year
- Workshop on Computer Architecture Research with RISC-V (CARRV)☆42Updated last year
- A scala based simulator for circuits described by a LoFirrtl file☆49Updated 2 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆37Updated 4 years ago
- ☆89Updated 4 months ago
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago