Alternatives and similar repositories for firechip

Users that are interested in firechip are comparing it to the libraries listed below

• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆82Updated 4 months ago
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆101Updated 5 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 5 months ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆148Updated 2 months ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 3 years ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆42Updated 7 years ago
• ucb-bar / testchipip
  ☆86Updated 4 months ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆72Updated 5 years ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆88Updated last year
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆85Updated 4 years ago
• riscv / riscv-test-env
  ☆50Updated last month
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆53Updated 5 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆66Updated 11 months ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆110Updated 2 years ago
• mit-ll / CEP
  The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…
  ☆66Updated 2 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆164Updated 5 years ago
• socrocket / core
  SoCRocket - Core Repository
  ☆38Updated 8 years ago
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆58Updated 11 months ago
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆32Updated last year
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago
• firesim / FireMarshal
  Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
  ☆86Updated last week
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆122Updated 2 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated last month
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 3 months ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆34Updated 2 years ago
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆104Updated 6 years ago
• ucb-bar / sha3
  ☆80Updated last year
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆67Updated 6 years ago