firesim / firechipLinks
Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.
☆57Updated 5 years ago
Alternatives and similar repositories for firechip
Users that are interested in firechip are comparing it to the libraries listed below
Sorting:
- OmniXtend cache coherence protocol☆82Updated 3 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆145Updated 3 weeks ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Original RISC-V 1.0 implementation. Not supported.☆41Updated 6 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- ☆50Updated 4 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 4 months ago
- A time-predictable processor for mixed-criticality systems☆59Updated 10 months ago
- ☆86Updated 2 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- A fault-injection framework using Chisel and FIRRTL☆37Updated 4 months ago
- A scala based simulator for circuits described by a LoFirrtl file☆50Updated 2 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆65Updated 2 years ago
- Lipsi: Probably the Smallest Processor in the World☆86Updated last year
- ☆64Updated 6 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆86Updated 11 months ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- SoCRocket - Core Repository☆38Updated 8 years ago
- For contributions of Chisel IP to the chisel community.☆65Updated 10 months ago
- RiscyOO: RISC-V Out-of-Order Processor☆161Updated 5 years ago
- Useful utilities for BAR projects☆32Updated last year
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆85Updated last week
- Provides dot visualizations of chisel/firrtl circuits☆121Updated 2 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last week
- FPGA tool performance profiling☆102Updated last year
- Firmware infrastructure, contain RTOS Abstraction Layer, demos and more...☆53Updated 3 years ago
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆163Updated 3 months ago