Flexible Intermediate Representation for RTL
☆748Aug 20, 2024Updated last year
Alternatives and similar repositories for firrtl
Users that are interested in firrtl are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Chisel: A Modern Hardware Design Language☆4,701Updated this week
- Chisel/Firrtl execution engine☆157Aug 21, 2024Updated last year
- Rocket Chip Generator☆3,803Jun 2, 2026Updated last month
- A scala based simulator for circuits described by a LoFirrtl file☆50Jan 12, 2023Updated 3 years ago
- Provides various testers for chisel users☆101Jan 12, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A Library of Chisel3 Tools for Digital Signal Processing☆248Apr 29, 2024Updated 2 years ago
- Circuit IR Compilers and Tools☆2,173Updated this week
- A template project for beginning new Chisel work☆702Feb 24, 2026Updated 4 months ago
- chisel tutorial exercises and answers☆753Jan 6, 2022Updated 4 years ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆234Aug 19, 2024Updated last year
- Provides dot visualizations of chisel/firrtl circuits☆123Apr 14, 2023Updated 3 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,309Jun 26, 2026Updated last week
- Digital Design with Chisel☆923Jun 15, 2026Updated 2 weeks ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,138Sep 10, 2024Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Simple RISC-V 3-stage Pipeline in Chisel☆615Aug 9, 2024Updated last year
- educational microarchitectures for risc-v isa☆749Sep 1, 2025Updated 10 months ago
- The specification for the FIRRTL language☆66Jun 23, 2026Updated last week
- Scala based HDL☆2,012Jun 20, 2026Updated 2 weeks ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,186Jun 26, 2026Updated last week
- Yosys Open SYnthesis Suite☆4,553Jun 27, 2026Updated last week
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,020Jun 26, 2026Updated last week
- magma circuits☆263Oct 19, 2024Updated last year
- Verilator open-source SystemVerilog simulator and lint system☆3,707Updated this week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆223Jan 23, 2020Updated 6 years ago
- XLS: Accelerated HW Synthesis☆1,503Updated this week
- Low Level Hardware Description — A foundation for building hardware design tools.☆434Apr 20, 2022Updated 4 years ago
- (System)Verilog to Chisel translator☆121May 20, 2022Updated 4 years ago
- Useful utilities for BAR projects☆31Jan 3, 2024Updated 2 years ago
- RISC-V Torture Test☆217Jul 11, 2024Updated last year
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆103Nov 22, 2019Updated 6 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆323Mar 6, 2026Updated 3 months ago
- ☆385Jun 14, 2026Updated 2 weeks ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A hardware compiler based on LLHD and CIRCT☆270Jun 30, 2025Updated last year
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,983Updated this week
- The root repo for lowRISC project and FPGA demos.☆600Aug 3, 2023Updated 2 years ago
- high-performance RTL simulator☆194Jun 19, 2024Updated 2 years ago
- A prototype GUI for chisel-development☆51Jun 9, 2020Updated 6 years ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,877Jun 22, 2026Updated last week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆475Jun 10, 2026Updated 3 weeks ago