Alternatives and similar repositories for ResearchNote

Users that are interested in ResearchNote are comparing it to the libraries listed below

• meton-robean / Vector_MulAdd_Accelerator
  vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
  ☆53Updated 5 years ago
• OpenXiangShan / GEM5
  ☆86Updated this week
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆64Updated last year
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 3 years ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆52Updated 5 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• OSCPU / ysyxSoC
  ☆86Updated last month
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆134Updated 2 years ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆68Updated 7 months ago
• chenhaoc / ESL_Learning
  some knowleage about SystemC/TLM etc.
  ☆25Updated 2 years ago
• OSCPU / chisel-playground
  ☆68Updated 4 months ago
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆148Updated 4 months ago
• TeCSAR-UNCC / gem5-SALAM
  ☆91Updated last year
• cry-daniel / Computer-Architecture-Learning
  ☆61Updated 2 years ago
• Shuiliusheng / gem5_riscv_ckpt
  small and independent checkpoint
  ☆11Updated last year
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆62Updated 2 years ago
• TYOD-SOC / RISCV-Accelerator
  ☆36Updated 6 years ago
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆18Updated last month
• OSCPU / yosys-sta
  ☆72Updated 2 months ago
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆179Updated 6 years ago
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆117Updated 6 months ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆102Updated 4 months ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆74Updated 5 years ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆89Updated 3 months ago
• PolyArch / dsa-framework
  Release of stream-specialization software/hardware stack.
  ☆122Updated 2 years ago
• RV-BOSC / OpenNoC
  ☆163Updated last month
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆41Updated last year
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆57Updated 3 years ago
• riscv-stc / riscv-matrix-project
  Top project for RISC-V Matrix extension proposal and related opensource implementations.
  ☆30Updated last year
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆60Updated 3 years ago