meton-robean / ResearchNoteLinks
通过issue和README来记录日常学习研究笔记 关注 机器学习系统,深度学习, LLVM,性能剖视, Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using github issue and markdown! (inculding Machine Learning algs and system, LLVM, Linux kernel, java, python, c++, golang)
☆78Updated 5 years ago
Alternatives and similar repositories for ResearchNote
Users that are interested in ResearchNote are comparing it to the libraries listed below
Sorting:
- ☆113Updated this week
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆53Updated 3 years ago
- A Study of the SiFive Inclusive L2 Cache☆69Updated last year
- Wrapper for Rocket-Chip on FPGAs☆138Updated 3 years ago
- Run rocket-chip on FPGA☆76Updated 2 weeks ago
- Comment on the rocket-chip source code☆179Updated 7 years ago
- Gem5 with chinese comment and introduction (master) and some other std gem5 version.☆42Updated 3 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆155Updated 9 months ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- ☆68Updated 9 months ago
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago
- RiVEC Bencmark Suite☆124Updated last year
- ☆89Updated 2 months ago
- XiangShan Frontend Develop Environment☆68Updated 2 weeks ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- ☆37Updated 7 years ago
- ☆81Updated last year
- GPGPU supporting RISCV-V, developed with verilog HDL☆124Updated 9 months ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆215Updated 2 weeks ago
- Modern co-simulation framework for RISC-V CPUs☆159Updated this week
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆59Updated 3 years ago
- Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated☆234Updated 10 months ago
- Release of stream-specialization software/hardware stack.☆119Updated 2 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆64Updated 2 years ago
- ☆86Updated 3 weeks ago
- Pick your favorite language to verify your chip.☆74Updated 3 weeks ago
- EDA wiki☆135Updated last month
- a training-target implementation of rv32im, designed to be simple and easy to understand☆61Updated 3 years ago
- A Chisel RTL generator for network-on-chip interconnects☆223Updated 3 weeks ago
- Collect some IC textbooks for learning.☆172Updated 3 years ago