meton-robean / ResearchNote
通过issue和README来记录日常学习研究笔记 关注 机器学习系统,深度学习, LLVM,性能剖视, Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using github issue and markdown! (inculding Machine Learning algs and system, LLVM, Linux kernel, java, python, c++, golang)
☆75Updated 4 years ago
Alternatives and similar repositories for ResearchNote:
Users that are interested in ResearchNote are comparing it to the libraries listed below
- ☆74Updated this week
- Gem5 with chinese comment and introduction (master) and some other std gem5 version.☆41Updated 3 years ago
- A Study of the SiFive Inclusive L2 Cache☆57Updated last year
- Wrapper for Rocket-Chip on FPGAs☆129Updated 2 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆51Updated 4 years ago
- ☆58Updated 2 years ago
- ☆89Updated last year
- GPGPU supporting RISCV-V, developed with verilog HDL☆83Updated 6 months ago
- Comment on the rocket-chip source code☆170Updated 6 years ago
- ☆36Updated 6 years ago
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆52Updated 4 years ago
- Modern co-simulation framework for RISC-V CPUs☆132Updated this week
- A matrix extension proposal for AI applications under RISC-V architecture☆124Updated this week
- ☆114Updated this week
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆58Updated last year
- a training-target implementation of rv32im, designed to be simple and easy to understand☆55Updated 3 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆47Updated 2 years ago
- Run rocket-chip on FPGA☆64Updated 3 months ago
- Release of stream-specialization software/hardware stack.☆120Updated last year
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆228Updated 2 years ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆137Updated 4 months ago
- RiVEC Bencmark Suite☆109Updated 2 months ago
- The official repository for the gem5 resources sources.☆64Updated this week
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆149Updated last year
- ☆59Updated last week
- Collect some IC textbooks for learning.☆121Updated 2 years ago
- An integrated CGRA design framework☆85Updated 3 months ago
- ☆38Updated 2 years ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆241Updated 3 months ago
- Unit tests generator for RVV 1.0☆74Updated last week