Alternatives and similar repositories for ResearchNote

Users that are interested in ResearchNote are comparing it to the libraries listed below

• OpenXiangShan / GEM5
  ☆98Updated this week
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆180Updated 6 years ago
• OSCPU / chisel-playground
  ☆67Updated 7 months ago
• meton-robean / Vector_MulAdd_Accelerator
  vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
  ☆54Updated 5 years ago
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 3 years ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆53Updated 5 years ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆137Updated 2 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 3 years ago
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆67Updated last year
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆73Updated 10 months ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆153Updated this week
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆121Updated 9 months ago
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆152Updated 7 months ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆207Updated 3 months ago
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆65Updated 2 weeks ago
• OSCPU / ysyxSoC
  ☆86Updated last week
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆110Updated 6 months ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆57Updated 3 years ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆66Updated this week
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• cry-daniel / Computer-Architecture-Learning
  ☆64Updated 2 years ago
• TYOD-SOC / RISCV-Accelerator
  ☆36Updated 6 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆209Updated 3 weeks ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆154Updated last year
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• pkuzjx / EDA-wiki
  EDA wiki
  ☆131Updated 5 months ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆179Updated 11 months ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆41Updated last year
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆61Updated 3 years ago
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆162Updated 3 years ago