meton-robean / ResearchNoteLinks
通过issue和README来记录日常学习研究笔记 关注 机器学习系统,深度学习, LLVM,性能剖视, Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using github issue and markdown! (inculding Machine Learning algs and system, LLVM, Linux kernel, java, python, c++, golang)
☆77Updated 5 years ago
Alternatives and similar repositories for ResearchNote
Users that are interested in ResearchNote are comparing it to the libraries listed below
Sorting:
- ☆104Updated last week
- Wrapper for Rocket-Chip on FPGAs☆137Updated 3 years ago
- A Study of the SiFive Inclusive L2 Cache☆67Updated last year
- Run rocket-chip on FPGA☆76Updated last week
- A matrix extension proposal for AI applications under RISC-V architecture☆153Updated 8 months ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆53Updated 3 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆54Updated 5 years ago
- Comment on the rocket-chip source code☆179Updated 7 years ago
- Gem5 with chinese comment and introduction (master) and some other std gem5 version.☆42Updated 3 years ago
- Pick your favorite language to verify your chip.☆70Updated last week
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago
- XiangShan Frontend Develop Environment☆67Updated last month
- RiVEC Bencmark Suite☆123Updated 10 months ago
- ☆87Updated 3 weeks ago
- Modern co-simulation framework for RISC-V CPUs☆159Updated last week
- ☆67Updated 8 months ago
- data preprocessing scripts for gem5 output☆19Updated 5 months ago
- ☆22Updated 2 years ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆212Updated 4 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- A Chisel RTL generator for network-on-chip interconnects☆212Updated 2 months ago
- An integrated CGRA design framework☆91Updated 7 months ago
- ☆83Updated 6 months ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆116Updated 8 months ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆155Updated last year
- Modeling Architectural Platform☆211Updated this week
- Release of stream-specialization software/hardware stack.☆120Updated 2 years ago
- gem5 FS模式实验手册☆44Updated 2 years ago
- ☆37Updated 6 years ago