Alternatives and similar repositories for playground

Users that are interested in playground are comparing it to the libraries listed below

• sequencer / arithmetic
  ☆33Updated last month
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆74Updated 5 years ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆81Updated 3 weeks ago
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆70Updated last year
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆150Updated 6 months ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆196Updated last week
• hushenwei2000 / rvv-atg
  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…
  ☆14Updated last year
• OSCPU / chisel-playground
  ☆67Updated 3 months ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆133Updated 2 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆153Updated last year
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆42Updated this week
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆109Updated 2 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆113Updated 2 years ago
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆177Updated 3 weeks ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆92Updated this week
• ucb-bar / chisel-gui
  A prototype GUI for chisel-development
  ☆52Updated 4 years ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆84Updated last month
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆233Updated 8 months ago
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆153Updated 8 months ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆65Updated 9 months ago
• chipsalliance / rocket-chip-inclusive-cache
  An RTL generator for a last-level shared inclusive TileLink cache controller
  ☆19Updated 3 months ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆55Updated 4 years ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆96Updated this week
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆67Updated 6 months ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆158Updated 10 months ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆174Updated this week
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆151Updated this week