Alternatives and similar repositories for playground

Users that are interested in playground are comparing it to the libraries listed below

• sequencer / arithmetic
  ☆33Updated 3 months ago
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆77Updated last year
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆86Updated last month
• ucb-bar / chisel-gui
  A prototype GUI for chisel-development
  ☆52Updated 5 years ago
• ucb-bar / sha3
  ☆81Updated last year
• chipsalliance / espresso
  ☆40Updated last month
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆109Updated 2 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆62Updated 3 years ago
• OSCPU / chisel-playground
  ☆67Updated 5 months ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 7 months ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆101Updated last month
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆43Updated this week
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆152Updated 8 months ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆168Updated last year
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆74Updated 5 years ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆119Updated 2 years ago
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆124Updated last year
• hushenwei2000 / rvv-atg
  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…
  ☆16Updated last year
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆115Updated 3 years ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆154Updated last year
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆88Updated 2 months ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆32Updated last year
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆135Updated 2 years ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 2 months ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆103Updated 2 months ago
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆180Updated 2 months ago
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆103Updated 3 months ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 3 years ago