chipyard in mill :P
☆77Nov 20, 2023Updated 2 years ago
Alternatives and similar repositories for playground
Users that are interested in playground are comparing it to the libraries listed below
Sorting:
- This repository is outdated and the related functionality has been migrated to https://github.com/easysoc/easysoc-firrtl☆11Nov 3, 2021Updated 4 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Feb 17, 2022Updated 4 years ago
- ☆33Mar 20, 2025Updated 11 months ago
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆20Nov 27, 2024Updated last year
- Dump Apple PMU counter definitions from `/usr/share/kpep` in macOS☆16Jan 8, 2026Updated last month
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Sep 9, 2021Updated 4 years ago
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 6 months ago
- Wrapper for Rocket-Chip on FPGAs☆137Oct 5, 2022Updated 3 years ago
- Implements kernels with RISC-V Vector☆22Mar 24, 2023Updated 2 years ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆33Apr 13, 2021Updated 4 years ago
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 3 months ago
- Paging Debug tool for GDB using python☆13Jun 4, 2022Updated 3 years ago
- A prototype GUI for chisel-development☆51Jun 9, 2020Updated 5 years ago
- A Chisel RTL generator for network-on-chip interconnects☆226Nov 7, 2025Updated 3 months ago
- A Library of Chisel3 Tools for Digital Signal Processing☆244Apr 29, 2024Updated last year
- Backend & Frontend for JieLabs☆22Mar 3, 2023Updated 3 years ago
- (System)Verilog to Chisel translator☆116May 20, 2022Updated 3 years ago
- ☆17Mar 17, 2022Updated 3 years ago
- Run Rocket Chip on VCU128☆30Oct 21, 2025Updated 4 months ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆233Aug 19, 2024Updated last year
- ☆10Nov 12, 2019Updated 6 years ago
- Generate Linux Perf event tables for Apple Silicon☆17Dec 16, 2025Updated 2 months ago
- The working draft to split rocket core out from rocket chip☆14Dec 22, 2023Updated 2 years ago
- A hand-written recursive decent Verilog parser.☆10Jan 30, 2026Updated last month
- Chisel/Firrtl execution engine☆155Aug 21, 2024Updated last year
- Remote JTAG server for remote debugging☆43Dec 31, 2025Updated 2 months ago
- Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program☆30Sep 17, 2025Updated 5 months ago
- ☆311Feb 6, 2026Updated 3 weeks ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆162Jan 25, 2024Updated 2 years ago
- Comment on the rocket-chip source code☆179Oct 19, 2018Updated 7 years ago
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated last year
- Amazon F1-inspired Xilinx VCU118 hardware design framework☆13Jan 4, 2021Updated 5 years ago
- RTL blocks compatible with the Rocket Chip Generator☆17Mar 30, 2025Updated 11 months ago
- ☆12May 20, 2021Updated 4 years ago
- ZC RISCV CORE☆12Dec 19, 2019Updated 6 years ago
- ☆87Jan 30, 2026Updated last month
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆313Feb 20, 2026Updated last week
- Open-source RISC-V cryptographic hardware token, RTL repo☆20Nov 9, 2022Updated 3 years ago
- 通过issue和README来记录日常学习研究笔记 关注 机器学习系统，深度学习， LLVM，性能剖视， Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …☆78May 24, 2020Updated 5 years ago