ccelio / riscv-boom-doc
Documentation for the BOOM processor
☆47Updated 7 years ago
Alternatives and similar repositories for riscv-boom-doc:
Users that are interested in riscv-boom-doc are comparing it to the libraries listed below
- educational microarchitectures for risc-v isa☆65Updated 5 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- ☆43Updated 3 weeks ago
- A template for building new projects/platforms using the BOOM core.☆24Updated 6 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆82Updated 3 years ago
- Lipsi: Probably the Smallest Processor in the World☆82Updated 9 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆79Updated 3 months ago
- Yet Another RISC-V Implementation☆86Updated 3 months ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆99Updated 6 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆92Updated 3 years ago
- Weekly RISC-V Newsletter☆28Updated 6 years ago
- Parallel Array of Simple Cores. Multicore processor.☆94Updated 5 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- Tests for example Rocket Custom Coprocessors☆69Updated 4 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- The OpenRISC 1000 architectural simulator☆72Updated 4 months ago
- CVA6 SDK containing RISC-V tools and Buildroot☆61Updated 6 months ago
- Riscy Processors - Open-Sourced RISC-V Processors☆72Updated 5 years ago
- FPGA reference design for the the Swerv EH1 Core☆69Updated 5 years ago
- Support for Rocket Chip on Zynq FPGAs☆39Updated 5 years ago
- Open Processor Architecture☆26Updated 8 years ago
- 👾 Design ∪ Hardware☆72Updated 2 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆163Updated 5 months ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 7 years ago
- OmniXtend cache coherence protocol☆78Updated 4 years ago
- A time-predictable processor for mixed-criticality systems☆57Updated 2 months ago
- A Style Guide for the Chisel Hardware Construction Language☆106Updated 3 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆60Updated 4 months ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆34Updated 3 years ago
- Original RISC-V 1.0 implementation. Not supported.☆41Updated 6 years ago