ccelio / riscv-boom-docLinks
Documentation for the BOOM processor
☆47Updated 8 years ago
Alternatives and similar repositories for riscv-boom-doc
Users that are interested in riscv-boom-doc are comparing it to the libraries listed below
Sorting:
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- A template for building new projects/platforms using the BOOM core.☆24Updated 6 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆101Updated 6 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- Open Processor Architecture☆26Updated 9 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 7 years ago
- ☆47Updated last month
- Support for Rocket Chip on Zynq FPGAs☆40Updated 6 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆66Updated last year
- The Shang high-level synthesis framework☆120Updated 11 years ago
- Lipsi: Probably the Smallest Processor in the World☆86Updated last year
- Consistency checker for memory subsystem traces☆22Updated 8 years ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆37Updated 3 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 4 years ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 8 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆175Updated last month
- Riscy Processors - Open-Sourced RISC-V Processors☆74Updated 6 years ago
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- ☆32Updated 7 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- LIS Network-on-Chip Implementation☆30Updated 8 years ago
- OmniXtend cache coherence protocol☆82Updated last week
- Workshop on Computer Architecture Research with RISC-V (CARRV)☆39Updated 7 months ago
- RISC-V Frontend Server☆63Updated 6 years ago