freechipsproject / chisel-bootcampLinks
Generator Bootcamp Material: Learn Chisel the Right Way
☆1,066Updated last year
Alternatives and similar repositories for chisel-bootcamp
Users that are interested in chisel-bootcamp are comparing it to the libraries listed below
Sorting:
- Digital Design with Chisel☆858Updated this week
- chisel tutorial exercises and answers☆736Updated 3 years ago
- A template project for beginning new Chisel work☆661Updated 3 months ago
- educational microarchitectures for risc-v isa☆719Updated last week
- Simple RISC-V 3-stage Pipeline in Chisel☆588Updated last year
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,959Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,112Updated 3 months ago
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆992Updated 3 weeks ago
- Random instruction generator for RISC-V processor verification☆1,159Updated 3 months ago
- RISC-V Cores, SoC platforms and SoCs☆896Updated 4 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,365Updated last week
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,963Updated 4 months ago
- Flexible Intermediate Representation for RTL☆747Updated last year
- 32-bit Superscalar RISC-V CPU☆1,091Updated 3 years ago
- OpenXuantie - OpenC910 Core☆1,311Updated last year
- VeeR EH1 core☆894Updated 2 years ago
- synthesiseable ieee 754 floating point library in verilog☆671Updated 2 years ago
- Scala based HDL☆1,847Updated this week
- The Ultra-Low Power RISC-V Core☆1,588Updated last month
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,628Updated last week
- The OpenPiton Platform☆729Updated 2 weeks ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆511Updated 9 months ago
- Support for Rocket Chip on Zynq FPGAs☆412Updated 6 years ago
- Common SystemVerilog components☆654Updated last week
- ☆1,053Updated 2 months ago
- RISC-V CPU Core (RV32IM)☆1,532Updated 3 years ago
- Verilog AXI components for FPGA implementation☆1,807Updated 6 months ago
- Functional verification project for the CORE-V family of RISC-V cores.☆590Updated last week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆933Updated 9 months ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆960Updated 2 months ago