freechipsproject / chisel-bootcampLinks
Generator Bootcamp Material: Learn Chisel the Right Way
☆1,074Updated last year
Alternatives and similar repositories for chisel-bootcamp
Users that are interested in chisel-bootcamp are comparing it to the libraries listed below
Sorting:
- chisel tutorial exercises and answers☆733Updated 3 years ago
- Digital Design with Chisel☆870Updated this week
- A template project for beginning new Chisel work☆668Updated last month
- Simple RISC-V 3-stage Pipeline in Chisel☆598Updated last year
- educational microarchitectures for risc-v isa☆723Updated 2 months ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,029Updated 2 weeks ago
- Random instruction generator for RISC-V processor verification☆1,189Updated last month
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,136Updated 5 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,397Updated 2 weeks ago
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆1,002Updated 2 months ago
- 32-bit Superscalar RISC-V CPU☆1,121Updated 4 years ago
- OpenXuantie - OpenC910 Core☆1,339Updated last year
- RISC-V Cores, SoC platforms and SoCs☆901Updated 4 years ago
- The Ultra-Low Power RISC-V Core☆1,640Updated 3 months ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,002Updated 6 months ago
- VeeR EH1 core☆904Updated 2 years ago
- RISC-V CPU Core (RV32IM)☆1,562Updated 4 years ago
- Flexible Intermediate Representation for RTL☆748Updated last year
- Scala based HDL☆1,871Updated this week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,657Updated last month
- ☆1,080Updated this week
- Verilog AXI components for FPGA implementation☆1,841Updated 8 months ago
- The OpenPiton Platform☆740Updated last month
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆519Updated 11 months ago
- synthesiseable ieee 754 floating point library in verilog☆688Updated 2 years ago
- Support for Rocket Chip on Zynq FPGAs☆412Updated 6 years ago
- Common SystemVerilog components☆672Updated 2 weeks ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆970Updated 4 months ago
- Verilog PCI express components☆1,453Updated last year
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆469Updated 3 months ago