Generator Bootcamp Material: Learn Chisel the Right Way
☆1,171Sep 21, 2026Updated last month
Alternatives and similar repositories for chisel-bootcamp
Users that are interested in chisel-bootcamp are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A template project for beginning new Chisel work☆710Feb 24, 2026Updated 8 months ago
- Digital Design with Chisel☆943Updated this week
- chisel tutorial exercises and answers☆758Jan 6, 2022Updated 4 years ago
- Chisel: A Modern Hardware Design Language☆4,825Updated this week
- Rocket Chip Generator☆3,894Sep 13, 2026Updated last month
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Chisel examples and code snippets☆288Aug 1, 2022Updated 4 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,442Updated this week
- A Library of Chisel3 Tools for Digital Signal Processing☆251Apr 29, 2024Updated 2 years ago
- educational microarchitectures for risc-v isa☆758Sep 1, 2025Updated last year
- Flexible Intermediate Representation for RTL☆748Aug 20, 2024Updated 2 years ago
- Simple RISC-V 3-stage Pipeline in Chisel☆620Aug 9, 2024Updated 2 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,274Oct 8, 2026Updated 3 weeks ago
- Provides various testers for chisel users☆101Jan 12, 2023Updated 3 years ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆234Aug 19, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Chisel/Firrtl execution engine☆157Aug 21, 2024Updated 2 years ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆239Jul 3, 2026Updated 3 months ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆225Jan 23, 2020Updated 6 years ago
- A Style Guide for the Chisel Hardware Construction Language☆110Jul 16, 2021Updated 5 years ago
- RISC-V SoC designed by students in UCAS☆1,561Updated this week
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,057Updated this week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,178Updated this week
- Open-source high-performance RISC-V processor☆7,357Updated this week
- Berkeley's Spatial Array Generator☆1,540Updated this week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Chisel Learning Journey☆109Apr 5, 2023Updated 3 years ago
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,854Mar 24, 2021Updated 5 years ago
- ☆73Oct 23, 2026Updated last week
- Comment on the rocket-chip source code☆179Oct 19, 2018Updated 8 years ago
- Scala based HDL☆2,053Oct 22, 2026Updated last week
- educational microarchitectures for risc-v isa☆68Feb 18, 2019Updated 7 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆329Aug 7, 2026Updated 2 months ago
- Provides dot visualizations of chisel/firrtl circuits☆123Apr 14, 2023Updated 3 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,301Oct 13, 2026Updated 2 weeks ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆166Jan 25, 2024Updated 2 years ago
- ☆86Jun 1, 2022Updated 4 years ago
- Common RTL blocks used in SiFive's projects☆194May 13, 2022Updated 4 years ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆970Updated this week
- Random instruction generator for RISC-V processor verification☆1,373Updated this week
- A dynamic verification library for Chisel.☆163Nov 9, 2024Updated last year
- ☆394Aug 19, 2026Updated 2 months ago