Helper scripts used to clone RISC-V related git repos inside China.
☆16Sep 17, 2020Updated 5 years ago
Alternatives and similar repositories for clone-helpers
Users that are interested in clone-helpers are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆10Nov 12, 2019Updated 6 years ago
- Comment on the rocket-chip source code☆179Oct 19, 2018Updated 7 years ago
- A Zero Cost Abstruction of FSM(Finite State Machine) circuits based on chisel3.☆13Oct 8, 2021Updated 4 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- ☆17Apr 3, 2022Updated 3 years ago
- A fork of the main Verilator project for development work. The changes here are in preparation for committing back to the main project.☆18Nov 26, 2014Updated 11 years ago
- ☆18Jul 9, 2025Updated 8 months ago
- Universal syntax script for all txt docs, logs and other types☆10Sep 21, 2017Updated 8 years ago
- Light-weight RISC-V RV32IMC microcontroller core.☆104Mar 4, 2017Updated 9 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- Chisel Cheatsheet☆35Apr 13, 2023Updated 2 years ago
- SpinalHDL documentation assets (pictures, slides, ...)☆32Dec 10, 2024Updated last year
- ☆13Jan 20, 2021Updated 5 years ago
- an open source uvm verification platform for e200 (riscv)☆29May 5, 2018Updated 7 years ago
- A prototype GUI for chisel-development☆51Jun 9, 2020Updated 5 years ago
- This repository is outdated and the related functionality has been migrated to https://github.com/easysoc/easysoc-firrtl☆11Nov 3, 2021Updated 4 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Apr 18, 2022Updated 3 years ago
- Portable C Compiler (CVS mirror)☆12Apr 9, 2012Updated 13 years ago
- Huffman encoder☆10Sep 8, 2013Updated 12 years ago
- An SoC with multiple RISC-V IMA processors.☆19Aug 1, 2018Updated 7 years ago
- This is my first trial project for designing RISC-V in Chisel☆17Apr 29, 2024Updated last year
- ☆22Feb 22, 2020Updated 6 years ago
- 第四届全国大学生嵌入式比赛SoC☆11Apr 1, 2022Updated 3 years ago
- ☆11Dec 23, 2025Updated 3 months ago
- Unity, UE4, Python, OSVR, all plugins will be in this repo !☆11Jul 18, 2018Updated 7 years ago
- ☆10Aug 12, 2021Updated 4 years ago
- ☆26Sep 3, 2020Updated 5 years ago
- The root repo for lowRISC project and FPGA demos.☆600Aug 3, 2023Updated 2 years ago
- 链家二手房挂牌价爬虫☆10Jul 6, 2022Updated 3 years ago
- ☆10Apr 8, 2021Updated 4 years ago
- ☆12Feb 15, 2024Updated 2 years ago
- soc integration script and integration smoke script☆24Sep 12, 2022Updated 3 years ago
- Comic Colorization with cGAN☆14Dec 19, 2018Updated 7 years ago
- A soft multimedia/graphics processor prototype in Chisel 3☆11May 3, 2023Updated 2 years ago
- SNN on FPGA☆12Apr 26, 2022Updated 3 years ago
- verilog/FPGA hardware description for very simple GPU☆16Apr 9, 2019Updated 6 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆65Jan 13, 2021Updated 5 years ago
- Wrapper for Rocket-Chip on FPGAs☆136Oct 5, 2022Updated 3 years ago
- symmetric clock tree synthesis for NTV IC design☆11May 8, 2022Updated 3 years ago