Alternatives and similar repositories for clone-helpers:

Users that are interested in clone-helpers are comparing it to the libraries listed below

• lingscale / cc01
  ☆31Updated last month
• watz0n / learn-rv32i-asap
  A Simple As Possible RISCV-32I core with debug module.
  ☆42Updated 5 years ago
• sequencer / arithmetic
  ☆33Updated last month
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆28Updated 5 years ago
• SchaffHub / RISC-Verdi
  Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.
  ☆30Updated 5 years ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆33Updated 2 years ago
• zhaishaomin / ring_network-based-multicore-
  多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency
  ☆23Updated 8 years ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆38Updated last year
• bwitherspoon / rv32cpu
  A RISC-V processor
  ☆13Updated 6 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆65Updated 9 months ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆54Updated 4 years ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆67Updated 5 months ago
• baochuquan / RISCV-MMU
  ☆14Updated 7 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 4 years ago
• pulp-platform / axi_llc
  ☆26Updated 2 weeks ago
• chipsalliance / tilelink
  ☆30Updated 4 months ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆39Updated 2 years ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆55Updated last year
• ljgibbslf / basic_cache_core
  ☆27Updated 4 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆61Updated last year
• meton-robean / Vector_MulAdd_Accelerator
  vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
  ☆51Updated 5 years ago
• TYOD-SOC / RISCV-Accelerator
  ☆36Updated 6 years ago
• freecores / jtag
  JTAG Test Access Port (TAP)
  ☆33Updated 10 years ago
• yaozhaosh / e200_opensource
  The Ultra-Low Power RISC Core
  ☆15Updated 4 years ago
• cassuto / nano-cpu32k
  Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
  ☆53Updated 8 months ago
• yaozhaosh / chisel-aes
  Chisel implementation of AES
  ☆23Updated 5 years ago
• redpanda3 / chisel-book
  Hardware design with Chisel
  ☆32Updated 2 years ago
• oscc-ip / sdram
  An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …
  ☆17Updated 3 weeks ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated 11 months ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago