Alternatives and similar repositories for chisel-style-guide

Users that are interested in chisel-style-guide are comparing it to the libraries listed below

• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆76Updated 9 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆151Updated 6 months ago
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆124Updated last year
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆109Updated 2 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆198Updated 3 weeks ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆74Updated 5 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆207Updated this week
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆175Updated 2 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆119Updated 4 years ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆66Updated 11 months ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 6 years ago
• chipsalliance / uvm-verilator
  ☆95Updated last year
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆63Updated last week
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆154Updated 3 weeks ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆119Updated 2 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆166Updated 6 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆64Updated 3 weeks ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆159Updated last week
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆129Updated last week
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆178Updated 6 months ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆65Updated 5 years ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆77Updated this week
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆55Updated 3 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆195Updated 10 months ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆61Updated last year
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆104Updated 2 years ago
• pulp-platform / fpu
  ☆49Updated 6 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆62Updated last year
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆88Updated 2 months ago