ccelio / chisel-style-guide
A Style Guide for the Chisel Hardware Construction Language
☆107Updated 3 years ago
Alternatives and similar repositories for chisel-style-guide:
Users that are interested in chisel-style-guide are comparing it to the libraries listed below
- A dynamic verification library for Chisel.☆146Updated 4 months ago
- Examples for creating AXI-interfaced peripherals in Chisel☆74Updated 9 years ago
- A Chisel RTL generator for network-on-chip interconnects☆184Updated this week
- A Fast, Low-Overhead On-chip Network☆181Updated 2 weeks ago
- Chisel Learning Journey☆108Updated last year
- ☆88Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆66Updated this week
- Tests for example Rocket Custom Coprocessors☆70Updated 5 years ago
- Vector processor for RISC-V vector ISA☆115Updated 4 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆61Updated 8 months ago
- Chisel components for FPGA projects☆121Updated last year
- Verilog Configurable Cache☆172Updated 3 months ago
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆88Updated 11 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 6 months ago
- Pure digital components of a UCIe controller☆55Updated last week
- Advanced Architecture Labs with CVA6☆54Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆135Updated last week
- Network on Chip Implementation written in SytemVerilog☆169Updated 2 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆59Updated last year
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆163Updated 3 months ago
- Altera Advanced Synthesis Cookbook 11.0☆100Updated last year
- Provides dot visualizations of chisel/firrtl circuits☆119Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆136Updated 3 weeks ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆50Updated 3 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆73Updated 7 years ago
- RISC-V Torture Test☆183Updated 8 months ago
- Basic floating-point components for RISC-V processors☆64Updated 5 years ago
- ☆124Updated 2 weeks ago
- Python packages providing a library for Verification Stimulus and Coverage☆119Updated 2 weeks ago