ucb-bar / hammer
Hammer: Highly Agile Masks Made Effortlessly from RTL
☆278Updated 2 weeks ago
Alternatives and similar repositories for hammer:
Users that are interested in hammer are comparing it to the libraries listed below
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆249Updated 2 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆318Updated this week
- VeeR EL2 Core☆274Updated last week
- Build Customized FPGA Implementations for Vivado☆315Updated this week
- Standard Cell Library based Memory Compiler using FF/Latch cells☆145Updated 10 months ago
- Network on Chip Implementation written in SytemVerilog☆174Updated 2 years ago
- SystemVerilog synthesis tool☆190Updated last month
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆171Updated 5 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆136Updated 7 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆217Updated last month
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆166Updated 5 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆488Updated 2 months ago
- Fabric generator and CAD tools☆178Updated 3 weeks ago
- ☆156Updated last month
- A complete open-source design-for-testing (DFT) Solution☆150Updated 6 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆570Updated last week
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆208Updated 6 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆252Updated this week
- A Chisel RTL generator for network-on-chip interconnects☆196Updated this week
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆131Updated last year
- A dynamic verification library for Chisel.☆148Updated 5 months ago
- ☆322Updated 7 months ago
- A Fast, Low-Overhead On-chip Network☆200Updated last week
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆267Updated 2 weeks ago
- Python packages providing a library for Verification Stimulus and Coverage☆120Updated 2 weeks ago
- RISC-V Torture Test☆193Updated 9 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆388Updated 3 weeks ago
- SystemRDL 2.0 language compiler front-end☆251Updated 2 months ago
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆322Updated last week