Hammer: Highly Agile Masks Made Effortlessly from RTL
☆328Aug 7, 2026Updated 2 months ago
Alternatives and similar repositories for hammer
Users that are interested in hammer are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,420Updated this week
- ☆13Feb 13, 2021Updated 5 years ago
- A fault-injection framework using Chisel and FIRRTL☆39Sep 17, 2025Updated last year
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- Chisel/Firrtl execution engine☆157Aug 21, 2024Updated 2 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆299Jun 18, 2026Updated 3 months ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆103Nov 22, 2019Updated 6 years ago
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,050Updated this week
- A Library of Chisel3 Tools for Digital Signal Processing☆250Apr 29, 2024Updated 2 years ago
- SKY130 SRAM macros generated by SRAM 22☆26Sep 24, 2026Updated 2 weeks ago
- An abstraction library for interfacing EDA tools☆802Sep 15, 2026Updated 3 weeks ago
- Useful utilities for BAR projects☆31Jan 3, 2024Updated 2 years ago
- Next generation CGRA generator☆119Updated this week
- An open-source static random access memory (SRAM) compiler.☆1,153Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Comment on the rocket-chip source code☆179Oct 19, 2018Updated 7 years ago
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆93Sep 24, 2026Updated 2 weeks ago
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆468Sep 10, 2026Updated last month
- Flexible Intermediate Representation for RTL☆747Aug 20, 2024Updated 2 years ago
- Modular hardware build system☆1,230Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆691Updated this week
- Hardware generator debugger☆79Feb 12, 2024Updated 2 years ago
- ☆113Feb 2, 2021Updated 5 years ago
- Common RTL blocks used in SiFive's projects☆194May 13, 2022Updated 4 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- magma circuits☆264Oct 19, 2024Updated last year
- Debuggable hardware generator☆71Feb 17, 2023Updated 3 years ago
- Database and Tool Framework for EDA☆128Jan 25, 2021Updated 5 years ago
- 👾 Design ∪ Hardware☆79Sep 17, 2026Updated 3 weeks ago
- Tile based architecture designed for computing efficiency, scalability and generality☆303Sep 20, 2026Updated 3 weeks ago
- ☆92Updated this week
- A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Si…☆304Updated this week
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆166Jan 25, 2024Updated 2 years ago
- Open-source FPGA research and prototyping framework.☆212Aug 8, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Provides dot visualizations of chisel/firrtl circuites☆13Mar 12, 2019Updated 7 years ago
- Fluid Pipelines☆11May 4, 2018Updated 8 years ago
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆456Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆475Updated this week
- chipyard in mill :P☆77Nov 20, 2023Updated 2 years ago
- Rocket Chip Generator☆3,885Sep 13, 2026Updated last month
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆242Updated this week