ucb-bar / hammerLinks
Hammer: Highly Agile Masks Made Effortlessly from RTL
☆285Updated 2 months ago
Alternatives and similar repositories for hammer
Users that are interested in hammer are comparing it to the libraries listed below
Sorting:
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆258Updated last week
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆181Updated 5 years ago
- Build Customized FPGA Implementations for Vivado☆330Updated this week
- Test suite designed to check compliance with the SystemVerilog standard.☆336Updated this week
- SystemVerilog synthesis tool☆204Updated 4 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆224Updated last week
- Advanced Interface Bus (AIB) die-to-die hardware open source☆140Updated 10 months ago
- ☆178Updated 4 months ago
- A Fast, Low-Overhead On-chip Network☆216Updated last week
- A dynamic verification library for Chisel.☆154Updated 8 months ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆204Updated last week
- Standard Cell Library based Memory Compiler using FF/Latch cells☆152Updated last month
- Tile based architecture designed for computing efficiency, scalability and generality☆263Updated last month
- Qflow full end-to-end digital synthesis flow for ASIC designs☆216Updated 9 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆171Updated 8 months ago
- ☆334Updated 10 months ago
- VeeR EL2 Core☆292Updated 2 weeks ago
- A Chisel RTL generator for network-on-chip interconnects☆207Updated 2 months ago
- ☆156Updated 3 years ago
- A complete open-source design-for-testing (DFT) Solution☆162Updated 2 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆516Updated 5 months ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆381Updated 3 weeks ago
- SystemRDL 2.0 language compiler front-end☆256Updated this week
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆138Updated last year
- Verilog Configurable Cache☆180Updated 8 months ago
- Logic synthesis and ABC based optimization☆49Updated 3 weeks ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆403Updated this week
- Code used in☆193Updated 8 years ago
- Network on Chip Implementation written in SytemVerilog☆186Updated 2 years ago
- magma circuits☆261Updated 9 months ago