Alternatives and similar repositories for hammer:

Users that are interested in hammer are comparing it to the libraries listed below

• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆306Updated this week
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆130Updated 3 months ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆240Updated last week
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆157Updated 2 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆240Updated 3 weeks ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆205Updated 2 months ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆138Updated 7 months ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆299Updated this week
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆257Updated this week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆176Updated this week
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆242Updated last week
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆164Updated 2 years ago
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆155Updated 4 years ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆125Updated 11 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆155Updated 3 weeks ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools
  ☆155Updated this week
• The-OpenROAD-Project / OPENROAD_USERS_READ_ME_FIRST
  OpenROAD users should look at this repository first for instructions on getting started
  ☆102Updated 3 years ago
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆266Updated 2 months ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆143Updated 2 months ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆377Updated last month
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆450Updated 2 months ago
• The-OpenROAD-Project / asap7
  ☆117Updated 6 months ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆182Updated last month
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆247Updated 10 months ago
• phanrahan / magma
  magma circuits
  ☆255Updated 2 months ago
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆351Updated this week
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆116Updated 3 months ago
• ucb-bar / berkeley-hardfloat
  ☆301Updated 4 months ago