librecores / riscv-sodor
educational microarchitectures for risc-v isa
☆66Updated 6 years ago
Alternatives and similar repositories for riscv-sodor:
Users that are interested in riscv-sodor are comparing it to the libraries listed below
- Yet Another RISC-V Implementation☆93Updated 7 months ago
- Examples for creating AXI-interfaced peripherals in Chisel☆74Updated 9 years ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆65Updated 10 months ago
- Chisel Learning Journey☆109Updated 2 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆83Updated 4 years ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- Lipsi: Probably the Smallest Processor in the World☆84Updated last year
- ☆92Updated last year
- RISC-V Verification Interface☆89Updated 2 months ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆60Updated 4 years ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆71Updated 2 weeks ago
- Provides various testers for chisel users☆100Updated 2 years ago
- RISCV model for Verilator/FPGA targets☆51Updated 5 years ago
- Chisel components for FPGA projects☆122Updated last year
- Platform Level Interrupt Controller☆40Updated 11 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆62Updated 11 months ago
- Network on Chip Implementation written in SytemVerilog☆174Updated 2 years ago
- A Fast, Low-Overhead On-chip Network☆200Updated last week
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated this week
- A demo system for Ibex including debug support and some peripherals☆63Updated this week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆105Updated this week
- Python packages providing a library for Verification Stimulus and Coverage☆120Updated 2 weeks ago
- A Tiny Processor Core☆108Updated last month
- Generic FIFO implementation with optional FWFT☆57Updated 4 years ago
- Provides dot visualizations of chisel/firrtl circuits☆119Updated 2 years ago
- A dynamic verification library for Chisel.☆148Updated 5 months ago
- Python wrapper for verilator model☆82Updated last year