chipsalliance / foundationLinks
Governance-related CHIPS Alliance documents, guides etc.
☆10Updated 2 years ago
Alternatives and similar repositories for foundation
Users that are interested in foundation are comparing it to the libraries listed below
Sorting:
- FPGA250 aboard the eFabless Caravel☆32Updated 5 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆49Updated last month
- ☆38Updated 3 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 7 months ago
- Source-Opened RISCV for Crypto☆18Updated 4 years ago
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Updated 4 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆29Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆37Updated 3 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆24Updated 4 years ago
- Bitstream relocation and manipulation tool.☆51Updated 3 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆18Updated 8 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆92Updated 6 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- ☆38Updated last year
- Zero to ASIC group submission for MPW2☆13Updated 10 months ago
- ☆13Updated 3 years ago
- Docker Development Environment for SpinalHDL☆20Updated last year
- submission repository for efabless mpw6 shuttle☆31Updated 2 years ago
- ☆27Updated 11 months ago
- ☆38Updated 3 years ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- Quick'n'dirty FuseSoC+cocotb example☆19Updated last year
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- ☆19Updated 5 years ago
- LunaPnR is a place and router for integrated circuits☆47Updated 6 months ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆24Updated 5 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Updated 2 years ago
- Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.☆18Updated 4 years ago
- Automatic SystemVerilog linting in github actions with the help of Verible☆36Updated last year
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year