chipsalliance / foundationLinks
Governance-related CHIPS Alliance documents, guides etc.
☆10Updated 2 years ago
Alternatives and similar repositories for foundation
Users that are interested in foundation are comparing it to the libraries listed below
Sorting:
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆46Updated 2 months ago
- FPGA250 aboard the eFabless Caravel☆30Updated 4 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆18Updated 8 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 6 months ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 8 months ago
- ☆38Updated 3 years ago
- Source-Opened RISCV for Crypto☆16Updated 3 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 3 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last month
- Gate-level visualization generator for SKY130-based chip designs.☆20Updated 4 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- ☆17Updated 9 months ago
- Virtual development board for HDL design☆42Updated 2 years ago
- Zero to ASIC group submission for MPW2☆13Updated 4 months ago
- Demo SoC for SiliconCompiler.☆60Updated 2 months ago
- ☆36Updated 9 months ago
- LunaPnR is a place and router for integrated circuits☆47Updated 3 weeks ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated last year
- An automatic clock gating utility☆50Updated 3 months ago
- Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.☆18Updated 3 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆90Updated 6 years ago
- RISC-V processor☆31Updated 3 years ago
- ☆70Updated 11 months ago
- Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns☆13Updated 4 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory…☆31Updated 6 years ago
- An implementation of RISC-V☆38Updated last month
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago