soDLA-publishment / soDLALinks
Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated
☆231Updated 8 months ago
Alternatives and similar repositories for soDLA
Users that are interested in soDLA are comparing it to the libraries listed below
Sorting:
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆164Updated 3 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆201Updated 5 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆156Updated last year
- A discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.☆144Updated 7 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆161Updated 6 years ago
- A Chisel RTL generator for network-on-chip interconnects☆215Updated 2 months ago
- NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and…☆230Updated 6 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆217Updated 5 years ago
- ☆65Updated 3 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆116Updated 8 months ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆284Updated 2 weeks ago
- Comment on the rocket-chip source code☆179Updated 7 years ago
- Virtual Platform for NVDLA☆153Updated 7 years ago
- Chisel components for FPGA projects☆127Updated 2 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆240Updated last year
- Pure digital components of a UCIe controller☆74Updated 2 weeks ago
- Deep Learning Accelerator (Convolution Neural Networks)☆194Updated 7 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆153Updated 8 months ago
- OpenSoC Fabric - A Network-On-Chip Generator☆172Updated 5 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆167Updated last year
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆35Updated last year
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- A DSL for Systolic Arrays☆82Updated 6 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆224Updated 2 years ago
- ☆199Updated 4 months ago
- An AXI4 crossbar implementation in SystemVerilog☆177Updated last month
- 通过issue和README来记录日常学习研究笔记 关注 机器学习系统,深度学习, LLVM,性能剖视, Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …☆77Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆105Updated 5 years ago
- ☆70Updated 6 years ago