Alternatives and similar repositories for diagrammer

Users that are interested in diagrammer are comparing it to the libraries listed below

• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆153Updated 9 months ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆151Updated 6 months ago
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆124Updated last year
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆174Updated 3 weeks ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆114Updated 3 years ago
• ucb-bar / dsptools
  A Library of Chisel3 Tools for Digital Signal Processing
  ☆236Updated last year
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆109Updated 2 years ago
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆101Updated 5 years ago
• ucb-bar / testchipip
  ☆84Updated last month
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆231Updated 9 months ago
• chipsalliance / uvm-verilator
  ☆95Updated last year
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆154Updated last year
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 6 years ago
• ucb-bar / berkeley-hardfloat
  ☆326Updated 8 months ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆251Updated 2 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆198Updated last month
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆156Updated 4 years ago
• SpinalHDL / SpinalWorkshop
  Labs to learn SpinalHDL
  ☆148Updated 11 months ago
• SpinalHDL / SpinalTemplateSbt
  A basic SpinalHDL project
  ☆86Updated 2 months ago
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆80Updated 4 years ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆76Updated 9 years ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆160Updated last week
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆94Updated 2 weeks ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆74Updated 5 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆195Updated 10 months ago
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆179Updated 6 years ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆66Updated 11 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆105Updated 3 weeks ago