Alternatives and similar repositories for t1:

Users that are interested in t1 are comparing it to the libraries listed below

• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆158Updated last month
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆170Updated this week
• SpinalHDL / NaxRiscv
  ☆275Updated this week
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆99Updated this week
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆148Updated this week
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆77Updated last month
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆246Updated last week
• space-mit / riscv-ime-extension-spec
  Following the RISC-V IME extension standard, and reusing Vector register resources, these instructions can bring more than a tenfold perf…
  ☆53Updated 6 months ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆219Updated last year
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆222Updated 3 months ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆139Updated this week
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆183Updated 8 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆230Updated this week
• tenstorrent / riscv_arch_tests
  Self checking RISC-V directed tests
  ☆102Updated last week
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆239Updated 3 weeks ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆82Updated last month
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆78Updated 3 weeks ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆273Updated last year
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆113Updated 3 months ago
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆231Updated 6 months ago
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆128Updated last month
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆105Updated this week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆459Updated last month
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆266Updated this week
• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆105Updated last week
• ucsc-vama / essent
  high-performance RTL simulator
  ☆153Updated 8 months ago
• ucb-bar / berkeley-hardfloat
  ☆309Updated 6 months ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆405Updated this week
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆181Updated last week
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆183Updated this week