chipsalliance / t1
The highest performace Cray-like RISC-V Vector in the world.
☆265Updated this week
Alternatives and similar repositories for t1:
Users that are interested in t1 are comparing it to the libraries listed below
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆162Updated 3 months ago
- Vector Acceleration IP core for RISC-V*☆177Updated 3 weeks ago
- ☆283Updated last month
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆255Updated last week
- Tile based architecture designed for computing efficiency, scalability and generality☆252Updated this week
- Instruction Set Generator initially contributed by Futurewei☆279Updated last year
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆223Updated last year
- RISC-V RV64GC emulator designed for RTL co-simulation☆229Updated 5 months ago
- Unit tests generator for RVV 1.0☆83Updated last month
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆488Updated 2 months ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆153Updated last week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆422Updated 2 weeks ago
- CORE-V Family of RISC-V Cores☆265Updated 2 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆105Updated this week
- ☆132Updated last year
- A Chisel RTL generator for network-on-chip interconnects☆196Updated this week
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆211Updated 3 weeks ago
- Chisel RISC-V Vector 1.0 Implementation☆96Updated this week
- RISC-V Architecture Profiles☆147Updated 2 months ago
- ☆322Updated 7 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆250Updated 2 weeks ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆235Updated 6 months ago
- A 256-RISC-V-core system with low-latency access into shared L1 memory.☆290Updated last week
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆212Updated 4 years ago
- A Linux-capable RISC-V multicore for and by the world☆690Updated last week
- Self checking RISC-V directed tests☆105Updated 2 months ago
- A matrix extension proposal for AI applications under RISC-V architecture☆139Updated 2 months ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆233Updated 8 months ago
- Modern co-simulation framework for RISC-V CPUs☆142Updated this week
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆194Updated last month