Alternatives and similar repositories for t1

Users that are interested in t1 are comparing it to the libraries listed below

• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆173Updated last week
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆181Updated 2 months ago
• SpinalHDL / NaxRiscv
  ☆293Updated 3 weeks ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆263Updated last month
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 8 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆271Updated this week
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆89Updated 2 weeks ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆168Updated last week
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆226Updated last year
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆113Updated this week
• space-mit / riscv-ime-extension-spec
  Following the RISC-V IME extension standard, and reusing Vector register resources, these instructions can bring more than a tenfold perf…
  ☆66Updated 11 months ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆106Updated 2 months ago
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆83Updated last year
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆283Updated 5 months ago
• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆120Updated 3 weeks ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆155Updated 3 years ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆125Updated this week
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆143Updated this week
• tenstorrent / riscv_arch_tests
  Self checking RISC-V directed tests
  ☆111Updated 2 months ago
• tenstorrent / whisper
  ☆52Updated 2 weeks ago
• pulp-platform / mempool
  A 256-RISC-V-core system with low-latency access into shared L1 memory.
  ☆300Updated last week
• ucb-bar / berkeley-hardfloat
  ☆334Updated 10 months ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆178Updated 2 months ago
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆160Updated 5 months ago
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆150Updated last year
• ucsc-vama / essent
  high-performance RTL simulator
  ☆168Updated last year
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆290Updated last year
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆516Updated 5 months ago
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆150Updated 5 months ago
• pulp-platform / snitch_cluster
  An energy-efficient RISC-V floating-point compute cluster.
  ☆98Updated last week