Alternatives and similar repositories for t1

Users that are interested in t1 are comparing it to the libraries listed below

• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆226Updated 3 weeks ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆200Updated last week
• SpinalHDL / NaxRiscv
  ☆306Updated 2 weeks ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆131Updated 4 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆276Updated last month
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆100Updated 3 months ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆229Updated 2 years ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆136Updated this week
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆238Updated last year
• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆143Updated 2 weeks ago
• tenstorrent / whisper
  ☆78Updated this week
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆317Updated this week
• tenstorrent / riscv_arch_tests
  Self checking RISC-V directed tests
  ☆119Updated 8 months ago
• pulp-platform / snitch_cluster
  An energy-efficient RISC-V floating-point compute cluster.
  ☆123Updated 3 weeks ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆93Updated 2 months ago
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆162Updated last year
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆162Updated 3 years ago
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆157Updated last week
• ucb-bar / berkeley-hardfloat
  ☆367Updated 5 months ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆146Updated this week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆306Updated 2 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆213Updated last year
• MoonbaseOtago / vroom
  VRoom! RISC-V CPU
  ☆516Updated last year
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆172Updated last week
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆171Updated this week
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆89Updated last year
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆324Updated 11 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆178Updated 3 weeks ago
• pulp-platform / mempool
  A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
  ☆313Updated this week
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆184Updated 9 months ago