Alternatives and similar repositories for t1

Users that are interested in t1 are comparing it to the libraries listed below

• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆163Updated 4 months ago
• SpinalHDL / NaxRiscv
  ☆287Updated 2 months ago
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆178Updated 3 weeks ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆257Updated 2 weeks ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆263Updated this week
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆158Updated this week
• tenstorrent / riscv_arch_tests
  Self checking RISC-V directed tests
  ☆108Updated 2 weeks ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆284Updated last year
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆224Updated last year
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 6 months ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆85Updated 2 weeks ago
• ucb-bar / berkeley-hardfloat
  ☆326Updated 8 months ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆98Updated 3 weeks ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆269Updated 3 months ago
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆232Updated 9 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆139Updated this week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆497Updated 3 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆108Updated this week
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆278Updated last week
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆195Updated 10 months ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆198Updated 3 weeks ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆174Updated 3 weeks ago
• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆115Updated 3 weeks ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆214Updated last week
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆152Updated 3 years ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆429Updated last week
• riscv-ovpsim / imperas-riscv-tests
  ☆175Updated last year
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆150Updated 3 months ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆159Updated 11 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆320Updated 5 months ago