Alternatives and similar repositories for VexiiRiscv:

Users that are interested in VexiiRiscv are comparing it to the libraries listed below

• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆127Updated last month
• SpinalHDL / NaxRiscv
  ☆275Updated last week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆67Updated 10 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆169Updated last week
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆170Updated 2 months ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆111Updated 2 years ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆226Updated 3 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆107Updated 4 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆224Updated this week
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆156Updated this week
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆64Updated 2 weeks ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆90Updated this week
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆101Updated 8 months ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆146Updated 3 months ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆74Updated 2 weeks ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆113Updated 4 years ago
• chipsalliance / uvm-verilator
  ☆87Updated last year
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆265Updated this week
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆133Updated last week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆177Updated this week
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆145Updated last week
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆243Updated 3 months ago
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆160Updated last week
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆118Updated last week
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆103Updated this week
• riscv-ovpsim / imperas-riscv-tests
  ☆168Updated last year
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆166Updated 6 months ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆204Updated 4 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆59Updated 3 months ago