Like VexRiscv, but, Harder, Better, Faster, Stronger
☆209Mar 16, 2026Updated last week
Alternatives and similar repositories for VexiiRiscv
Users that are interested in VexiiRiscv are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆309Jan 23, 2026Updated 2 months ago
- A Rocket-based RISC-V superscalar in-order core☆38Mar 11, 2026Updated 2 weeks ago
- Open-source non-blocking L2 cache☆55Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,075Feb 11, 2026Updated last month
- ☆16Updated this week
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆502Mar 16, 2026Updated last week
- A Linux-capable RISC-V multicore for and by the world☆784Updated this week
- ☆19Aug 27, 2022Updated 3 years ago
- Chisel RISC-V Vector 1.0 Implementation☆138Mar 18, 2026Updated last week
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆85Jan 28, 2026Updated last month
- ☆21May 8, 2025Updated 10 months ago
- A Fast, Low-Overhead On-chip Network☆272Updated this week
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆17Feb 29, 2024Updated 2 years ago
- SpinalHDL Hardware Math Library☆97Jul 12, 2024Updated last year
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆61Jan 7, 2026Updated 2 months ago
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 3 months ago
- SoC based on VexRiscv and ICE40 UP5K☆161Mar 16, 2025Updated last year
- SpinalHDL components for Corundum Ethernet☆15Aug 16, 2023Updated 2 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55May 10, 2021Updated 4 years ago
- RISCV lock-step checker based on Spike☆14Mar 6, 2026Updated 2 weeks ago
- 32-bit Superscalar RISC-V CPU☆1,197Sep 18, 2021Updated 4 years ago
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,157Feb 21, 2026Updated last month
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆128Jul 11, 2025Updated 8 months ago
- List of SpinalHDL projects, libraries, and learning resources.☆25Jan 6, 2026Updated 2 months ago
- Scala based HDL☆1,935Mar 16, 2026Updated last week
- Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware☆13Aug 24, 2020Updated 5 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆20Nov 9, 2025Updated 4 months ago
- Repository containing ULX3S blink LED binaries☆13May 16, 2022Updated 3 years ago
- ☆312Mar 14, 2026Updated last week
- ☆59Mar 31, 2025Updated 11 months ago
- A Risc-V SoC for Tiny Tapeout☆51Dec 2, 2025Updated 3 months ago
- Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from ht…☆522Apr 8, 2024Updated last year
- Labs to learn SpinalHDL☆156Jul 4, 2024Updated last year
- A simple superscalar out-of-order RISC-V microprocessor☆239Feb 24, 2025Updated last year
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆68Jan 8, 2024Updated 2 years ago
- Scalable Interface for RISC-V ISA Extensions☆23Mar 16, 2026Updated last week
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆53Feb 2, 2026Updated last month
- SERV - The SErial RISC-V CPU☆1,766Feb 19, 2026Updated last month
- Spen's Official OpenOCD Mirror☆51Mar 10, 2025Updated last year