SpinalHDL / VexiiRiscvLinks
Like VexRiscv, but, Harder, Better, Faster, Stronger
☆190Updated this week
Alternatives and similar repositories for VexiiRiscv
Users that are interested in VexiiRiscv are comparing it to the libraries listed below
Sorting:
- ☆301Updated last month
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 5 months ago
- RISC-V Formal Verification Framework☆170Updated this week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆307Updated last week
- SystemVerilog synthesis tool☆220Updated 9 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated last week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆189Updated 3 months ago
- Labs to learn SpinalHDL☆151Updated last year
- ☆190Updated 2 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆221Updated 5 years ago
- Generic Register Interface (contains various adapters)☆133Updated last month
- RISC-V Torture Test☆204Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆102Updated 2 weeks ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆130Updated last week
- A Fast, Low-Overhead On-chip Network☆251Updated last week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆175Updated this week
- Verilog Configurable Cache☆187Updated 2 weeks ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated last month
- ☆120Updated 4 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆249Updated last year
- RISC-V System on Chip Template☆159Updated 4 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆180Updated 7 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆129Updated 2 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated last year
- Open-source RISC-V microcontroller for embedded and FPGA applications☆189Updated last week
- A dynamic verification library for Chisel.☆159Updated last year
- SystemVerilog frontend for Yosys☆181Updated last week
- ☆110Updated last month
- RISC-V RV64GC emulator designed for RTL co-simulation☆236Updated last year
- WAL enables programmable waveform analysis.☆163Updated last month