SpinalHDL / VexiiRiscv
Like VexRiscv, but, Harder, Better, Faster, Stronger
☆148Updated this week
Alternatives and similar repositories for VexiiRiscv:
Users that are interested in VexiiRiscv are comparing it to the libraries listed below
- A Fast, Low-Overhead On-chip Network☆181Updated last week
- RISC-V Formal Verification Framework☆129Updated this week
- ☆275Updated this week
- Verilog Configurable Cache☆172Updated 3 months ago
- A dynamic verification library for Chisel.☆146Updated 4 months ago
- (System)Verilog to Chisel translator☆111Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆78Updated this week
- SystemVerilog synthesis tool☆180Updated this week
- 64-bit multicore Linux-capable RISC-V processor☆85Updated 6 months ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆210Updated 4 years ago
- Open source high performance IEEE-754 floating unit☆67Updated last year
- ☆88Updated last year
- Opensource DDR3 Controller☆276Updated this week
- A RISC-V Core (RV32I) written in Chisel HDL☆102Updated 9 months ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆99Updated this week
- Generic Register Interface (contains various adapters)☆110Updated 5 months ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆88Updated 11 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆134Updated 2 weeks ago
- ☆168Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆169Updated 7 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆246Updated last week
- Labs to learn SpinalHDL☆147Updated 8 months ago
- Vector processor for RISC-V vector ISA☆115Updated 4 years ago
- RISC-V System on Chip Template☆156Updated this week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆230Updated last week
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 6 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆246Updated 4 months ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆59Updated last year
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆225Updated 4 months ago