SpinalHDL / VexiiRiscvLinks
Like VexRiscv, but, Harder, Better, Faster, Stronger
☆179Updated last week
Alternatives and similar repositories for VexiiRiscv
Users that are interested in VexiiRiscv are comparing it to the libraries listed below
Sorting:
- ☆296Updated last week
- RISC-V Formal Verification Framework☆150Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 2 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆245Updated 10 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆286Updated this week
- SystemVerilog synthesis tool☆211Updated 6 months ago
- ☆189Updated last year
- ☆108Updated last month
- Verilog Configurable Cache☆183Updated 10 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆118Updated this week
- RISC-V Torture Test☆197Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆183Updated last week
- RISC-V System on Chip Template☆159Updated last month
- Generic Register Interface (contains various adapters)☆130Updated last month
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆218Updated 5 years ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆217Updated last week
- RISC-V RV64GC emulator designed for RTL co-simulation☆230Updated 10 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 4 months ago
- A Fast, Low-Overhead On-chip Network☆228Updated this week
- Tile based architecture designed for computing efficiency, scalability and generality☆266Updated last week
- 64-bit multicore Linux-capable RISC-V processor☆97Updated 5 months ago
- Labs to learn SpinalHDL☆149Updated last year
- CORE-V Family of RISC-V Cores☆299Updated 7 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆95Updated this week
- WAL enables programmable waveform analysis.☆157Updated 3 months ago
- RISC-V microcontroller IP core developed in Verilog☆183Updated 5 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆140Updated last month
- SystemVerilog frontend for Yosys☆165Updated this week
- Main page☆128Updated 5 years ago