A Rocket-based RISC-V superscalar in-order core
☆42Aug 28, 2026Updated this week
Alternatives and similar repositories for shuttle
Users that are interested in shuttle are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Chisel RISC-V Vector 1.0 Implementation☆157Updated this week
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆39Dec 23, 2021Updated 4 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆167Updated this week
- A Heterogeneous GPU Platform for AI and Neural Graphics☆67Aug 13, 2026Updated 2 weeks ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆15Dec 23, 2022Updated 3 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- RTL blocks compatible with the Rocket Chip Generator☆17Mar 30, 2025Updated last year
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆45Sep 21, 2022Updated 3 years ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆262Aug 18, 2026Updated last week
- Proposed RISC-V Composable Custom Extensions Specification☆71Jun 28, 2025Updated last year
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆247Updated this week
- An implementation of RISC-V☆54Jul 14, 2026Updated last month
- Original test vector of RISC-V Vector Extension☆14Mar 23, 2021Updated 5 years ago
- Unit tests generator for RVV 1.0☆116May 25, 2026Updated 3 months ago
- ☆42Dec 8, 2024Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Simple library for decoding RISC-V instructions☆23Jun 21, 2026Updated 2 months ago
- A Library of Chisel3 Tools for Digital Signal Processing☆250Apr 29, 2024Updated 2 years ago
- ☆325Jan 23, 2026Updated 7 months ago
- A submodule of Chipyard https://github.com/ucb-bar/chipyard☆21Apr 28, 2026Updated 4 months ago
- Basic floating-point components for RISC-V processors☆69Dec 4, 2019Updated 6 years ago
- verification of simple axi-based cache☆19May 14, 2019Updated 7 years ago
- high-performance RTL simulator☆195Aug 4, 2026Updated 3 weeks ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆41Feb 6, 2024Updated 2 years ago
- An open silicon CHERIoT Ibex microcontroller chip☆19May 23, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆25Nov 9, 2025Updated 9 months ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,370Aug 19, 2026Updated last week
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆166Jan 25, 2024Updated 2 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆113Aug 19, 2026Updated last week
- A simple utility for doing RISC-V HPM perf monitoring.☆18May 8, 2017Updated 9 years ago
- Open source high performance IEEE-754 floating unit☆99Feb 26, 2024Updated 2 years ago
- Open-source non-blocking L2 cache☆65Updated this week
- Template Verilator project for beginners☆13Feb 2, 2023Updated 3 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 12 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- TASTy Migration Manager☆12Oct 9, 2025Updated 10 months ago
- ☆14Jul 16, 2026Updated last month
- ☆28Feb 28, 2026Updated 6 months ago
- ☆48Updated this week
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆39Mar 26, 2024Updated 2 years ago
- ☆92Aug 14, 2026Updated 2 weeks ago
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Nov 26, 2020Updated 5 years ago