A Rocket-based RISC-V superscalar in-order core
☆42Oct 16, 2026Updated 2 weeks ago
Alternatives and similar repositories for shuttle
Users that are interested in shuttle are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Chisel RISC-V Vector 1.0 Implementation☆159Updated this week
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆39Dec 23, 2021Updated 4 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely…☆26Sep 26, 2024Updated 2 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆179Updated this week
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆45Sep 21, 2022Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- RTL blocks compatible with the Rocket Chip Generator☆17Mar 30, 2025Updated last year
- 📸 ADCs for faster image sensors☆13Updated this week
- A Heterogeneous GPU Platform for AI and Neural Graphics☆71Updated this week
- Proposed RISC-V Composable Custom Extensions Specification☆74Jun 28, 2025Updated last year
- ☆328Jan 23, 2026Updated 9 months ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆15Dec 23, 2022Updated 3 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆166Jan 25, 2024Updated 2 years ago
- ☆21Mar 3, 2026Updated 7 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆122Oct 16, 2026Updated 2 weeks ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆264Oct 12, 2026Updated 2 weeks ago
- An implementation of RISC-V☆55Jul 14, 2026Updated 3 months ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆267Updated this week
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆41Feb 6, 2024Updated 2 years ago
- Simple library for decoding RISC-V instructions☆23Jun 21, 2026Updated 4 months ago
- Unit tests generator for RVV 1.0☆118May 25, 2026Updated 5 months ago
- MLIR-in as a compiler stack for ucb-bar☆21Updated this week
- ☆15Jul 28, 2026Updated 3 months ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆107Jun 24, 2025Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆324Jul 22, 2026Updated 3 months ago
- A submodule of Chipyard https://github.com/ucb-bar/chipyard☆21Oct 10, 2026Updated 2 weeks ago
- Original test vector of RISC-V Vector Extension☆14Mar 23, 2021Updated 5 years ago
- Basic floating-point components for RISC-V processors☆69Dec 4, 2019Updated 6 years ago
- verification of simple axi-based cache☆19May 14, 2019Updated 7 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆251Apr 29, 2024Updated 2 years ago
- ☆42Dec 8, 2024Updated last year
- An open silicon CHERIoT Ibex microcontroller chip☆19May 23, 2025Updated last year
- high-performance RTL simulator☆196Aug 4, 2026Updated 2 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,442Updated this week
- ET Accelerator Firmware and Runtime☆55Jul 17, 2026Updated 3 months ago
- ☆394Aug 19, 2026Updated 2 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆560Oct 16, 2026Updated 2 weeks ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆26Updated this week
- 🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation☆13Apr 30, 2026Updated 6 months ago
- Open source high performance IEEE-754 floating unit☆100Feb 26, 2024Updated 2 years ago