chipsalliance / chisel-interfaceLinks
The 'missing header' for Chisel
☆20Updated 3 months ago
Alternatives and similar repositories for chisel-interface
Users that are interested in chisel-interface are comparing it to the libraries listed below
Sorting:
- ☆33Updated 3 months ago
- Run Rocket Chip on VCU128☆30Updated 7 months ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Updated 3 years ago
- ☆17Updated 3 years ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆29Updated 5 months ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆43Updated 11 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- Wrappers for open source FPU hardware implementations.☆32Updated last year
- chipyard in mill :P☆78Updated last year
- This is an IDE for YSYX_NPC debuging☆12Updated 7 months ago
- A prototype GUI for chisel-development☆52Updated 5 years ago
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Updated 6 years ago
- ☆40Updated last month
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- This repo includes XiangShan's function units☆26Updated last week
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆28Updated 5 years ago
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆39Updated this week
- RISC-V 64 CPU☆10Updated 2 years ago
- ☆39Updated this week
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆17Updated this week
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆19Updated last month
- Basic chisel difftest environment for RTL design (WIP☆18Updated 4 months ago
- Open source high performance IEEE-754 floating unit☆77Updated last year
- Open-source high-performance non-blocking cache☆86Updated last month
- ☆67Updated 5 months ago
- Pick your favorite language to verify your chip.☆51Updated this week
- 本项目已被合并至官方Chiplab中☆12Updated 6 months ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆18Updated 2 months ago
- An RTL generator for a last-level shared inclusive TileLink cache controller☆20Updated 5 months ago
- CQU Dual Issue Machine☆35Updated last year