The 'missing header' for Chisel
☆24Feb 5, 2026Updated 8 months ago
Alternatives and similar repositories for chisel-interface
Users that are interested in chisel-interface are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- FrontEnd Reverse-engineering Toolkit - CPU frontend uarch research framework☆14Updated this week
- Craft your EDA toolchain with GRH IR☆21Updated this week
- ☆37Mar 20, 2025Updated last year
- Nix template for the chisel-based industrial designing flows.☆58Jul 21, 2026Updated 3 months ago
- ☆15Jul 28, 2026Updated 3 months ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- ☆90Oct 23, 2026Updated last week
- ☆73Oct 23, 2026Updated last week
- MCP server to read waveform files☆48Updated this week
- ☆17Apr 3, 2022Updated 4 years ago
- The Scala parser to parse riscv/riscv-opcodes generate☆26Jan 21, 2026Updated 9 months ago
- ☆17Mar 17, 2022Updated 4 years ago
- SPIREG - SPI slave logic for register access☆11Nov 12, 2025Updated 11 months ago
- Documentation for XiangShan Design☆54Updated this week
- ☆85Oct 29, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Open source high performance IEEE-754 floating unit☆100Feb 26, 2024Updated 2 years ago
- ☆12Sep 18, 2024Updated 2 years ago
- Xiangshan deterministic workloads generator☆29Oct 14, 2026Updated 2 weeks ago
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆81Oct 13, 2026Updated 2 weeks ago
- Open-source high-performance non-blocking cache☆102Jun 17, 2026Updated 4 months ago
- 给NEMU移植Linux Kernel!☆23Jun 1, 2025Updated last year
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆40Oct 8, 2026Updated 3 weeks ago
- Modern co-simulation framework for RISC-V CPUs☆191Updated this week
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- MIPS R10000 architecture simulator with C++☆11Jun 8, 2023Updated 3 years ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆147Updated this week
- MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.☆12Dec 27, 2022Updated 3 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆22May 12, 2025Updated last year
- A fork of Xiangshan for AI☆64Updated this week
- ☆324Jul 22, 2026Updated 3 months ago
- ☆10Sep 8, 2023Updated 3 years ago
- ☆52Jan 16, 2025Updated last year
- A hand-written recursive decent Verilog parser.☆10Jun 28, 2026Updated 4 months ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- VSH（SHell for Visualizing vcd file）项目为数字波形文件命令行查看器。☆25Dec 8, 2025Updated 10 months ago
- ☆17Aug 26, 2025Updated last year
- ☆28Dec 4, 2025Updated 10 months ago
- 适用于龙芯杯团队赛入门选手的应急cache模块☆38Mar 13, 2024Updated 2 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆24Nov 24, 2025Updated 11 months ago
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 4 years ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Sep 9, 2021Updated 5 years ago