The 'missing header' for Chisel
☆24Feb 5, 2026Updated 6 months ago
Alternatives and similar repositories for chisel-interface
Users that are interested in chisel-interface are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Craft your EDA toolchain with GRH IR☆19Updated this week
- ☆37Mar 20, 2025Updated last year
- Nix template for the chisel-based industrial designing flows.☆58Jul 21, 2026Updated last month
- ☆15Jul 28, 2026Updated last month
- ☆80Updated this week
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- ☆71Aug 16, 2026Updated 2 weeks ago
- MCP server to read waveform files☆47Aug 1, 2026Updated 3 weeks ago
- The Scala parser to parse riscv/riscv-opcodes generate☆26Jan 21, 2026Updated 7 months ago
- Documentation for XiangShan Design☆51Updated this week
- ☆17Mar 17, 2022Updated 4 years ago
- ☆83Oct 29, 2024Updated last year
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- Open source high performance IEEE-754 floating unit☆99Feb 26, 2024Updated 2 years ago
- Xiangshan deterministic workloads generator☆28May 14, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆77Updated this week
- Open-source high-performance non-blocking cache☆101Jun 17, 2026Updated 2 months ago
- A fork of Xiangshan for AI☆57Updated this week
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆22May 12, 2025Updated last year
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆39Jan 26, 2026Updated 7 months ago
- MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.☆12Dec 27, 2022Updated 3 years ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆142Aug 23, 2026Updated last week
- VSH（SHell for Visualizing vcd file）项目为数字波形文件命令行查看器。☆25Dec 8, 2025Updated 8 months ago
- 给NEMU移植Linux Kernel!☆23Jun 1, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆52Jan 16, 2025Updated last year
- MIPS R10000 architecture simulator with C++☆11Jun 8, 2023Updated 3 years ago
- ☆16Aug 26, 2025Updated last year
- ☆320Jul 22, 2026Updated last month
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆62Oct 27, 2024Updated last year
- Modern co-simulation framework for RISC-V CPUs☆182Updated this week
- A hand-written recursive decent Verilog parser.☆10Jun 28, 2026Updated 2 months ago
- 适用于龙芯杯团队赛入门选手的应急cache模块☆38Mar 13, 2024Updated 2 years ago
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Sep 9, 2021Updated 4 years ago
- jyy os enhanced☆13Jul 10, 2025Updated last year
- ☆28Dec 4, 2025Updated 8 months ago
- A Customized ASIC framework for Retro Stuff☆31Updated this week
- This project proposes a distributed communication protocol called MPIQ (Classical-Quantum Message Passing Interface) for the "classical +…☆15Apr 2, 2026Updated 4 months ago
- My RV64 CPU (Work in progress)☆19Dec 22, 2022Updated 3 years ago
- ☆20Mar 18, 2022Updated 4 years ago