Alternatives and similar repositories for chisel-interface

Users that are interested in chisel-interface are comparing it to the libraries listed below

• sequencer / arithmetic
  ☆33Updated 4 months ago
• 1932287243 / NPC_IDE
  This is an IDE for YSYX_NPC debuging
  ☆12Updated 7 months ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆33Updated last year
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆19Updated 2 months ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 8 months ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆62Updated 3 years ago
• nhynes / chisel3-axi
  Chisel3 AXI4-{Lite, Full, Stream} Definitions
  ☆15Updated 6 years ago
• oscc-ip / sdram
  An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …
  ☆19Updated 2 months ago
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆28Updated 5 years ago
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆30Updated 5 months ago
• oscc-web / ysyx-website
  The official website of One Student One Chip project.
  ☆10Updated last week
• chipsalliance / playground
  chipyard in mill :P
  ☆78Updated last year
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• OpenXiangShan / gsim
  ☆44Updated this week
• chipsalliance / espresso
  ☆40Updated last month
• Seeker0472 / ysyx-linux
  给NEMU移植Linux Kernel!
  ☆18Updated 2 months ago
• sequencer / zaozi
  A eDSL framework based on Scala and MLIR, focusing on the Hardware design.
  ☆48Updated last week
• iscas-tis / chisel-formal-verification
  Formal verification tools for Chisel and RISC-V
  ☆13Updated last year
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆87Updated 2 months ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆60Updated this week
• arch-simulator-sig / chisel-env
  Basic chisel difftest environment for RTL design (WIP
  ☆18Updated 4 months ago
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆44Updated last year
• OpenXiangShan / xfuzz
  Fuzzing General-Purpose Hardware Designs with Software Fuzzers
  ☆20Updated 3 weeks ago
• pku-liang / ksim
  ☆44Updated 6 months ago
• XS-MLVP / Example-NutShellCache
  开放验证平台NutShell Cache验证案例
  ☆8Updated 4 months ago
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆40Updated last year
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆46Updated last week
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• xunqianxun / liguoqi-rv64-cpu
  RISC-V 64 CPU
  ☆10Updated 2 years ago