upstream: https://github.com/RALC88/gem5
☆33May 30, 2023Updated 2 years ago
Alternatives and similar repositories for plct-gem5
Users that are interested in plct-gem5 are comparing it to the libraries listed below
Sorting:
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆11Aug 3, 2022Updated 3 years ago
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Nov 26, 2020Updated 5 years ago
- RTL blocks compatible with the Rocket Chip Generator☆17Mar 30, 2025Updated 11 months ago
- A Rocket-based RISC-V superscalar in-order core☆38Updated this week
- Formal verification tools for Chisel and RISC-V☆13Jul 2, 2024Updated last year
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Dec 31, 2018Updated 7 years ago
- ☆17Mar 8, 2025Updated 11 months ago
- Library of example SystemC/TLM peripherals for various SoCs based on the SCS library☆14Feb 8, 2026Updated 3 weeks ago
- A translator from ARM NEON intrinsics to RISCV-V Extension implementation☆41Aug 25, 2025Updated 6 months ago
- CV32E40X Design-Verification environment☆16Mar 25, 2024Updated last year
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆20Nov 27, 2024Updated last year
- ☆17Apr 3, 2022Updated 3 years ago
- ☆17May 9, 2022Updated 3 years ago
- XiangShan Frontend Develop Environment☆68Updated this week
- Chisel RISC-V Vector 1.0 Implementation☆133Updated this week
- ☆310Feb 6, 2026Updated 3 weeks ago
- Light weight threading library for gem5 syscall emulator (git mirror)☆16Mar 1, 2017Updated 9 years ago
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆23Feb 19, 2025Updated last year
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆144Jan 27, 2026Updated last month
- Examine and discover LoongArch instructions☆22Jul 11, 2025Updated 7 months ago
- RiVEC Bencmark Suite☆127Nov 27, 2024Updated last year
- FIPS 202 compliant SHA-3 core in Verilog☆23Oct 8, 2020Updated 5 years ago
- Unit tests generator for RVV 1.0☆103Nov 11, 2025Updated 3 months ago
- RISC-V Summit China 2023☆40Sep 27, 2023Updated 2 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Nov 24, 2025Updated 3 months ago
- Yocto project for Xuantie RISC-V CPU☆40Aug 8, 2025Updated 6 months ago
- Instruction Set Generator initially contributed by Futurewei☆306Oct 17, 2023Updated 2 years ago
- Run SPEC CPU2006 on Linux with either an Intel, ARM, or PowerPC processors.☆26Apr 25, 2018Updated 7 years ago
- ☆23Mar 4, 2025Updated 11 months ago
- Xtext project to parse CoreDSL files☆24Oct 17, 2025Updated 4 months ago
- A concolic testing engine for RISC-V embedded software with support for SystemC peripherals☆27Oct 4, 2023Updated 2 years ago
- ULPI Link Wrapper (USB Phy Interface)☆35May 3, 2020Updated 5 years ago
- Monorepo containing a machine-readable database of the RISC-V specification and artifact generation tools☆161Updated this week
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated this week
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆36Jan 26, 2026Updated last month
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆490Nov 27, 2025Updated 3 months ago
- Run Rocket Chip on VCU128☆30Oct 21, 2025Updated 4 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆34Dec 11, 2025Updated 2 months ago
- PoC LoongArch - RISC-V emulator☆33Feb 17, 2026Updated last week