Modern co-simulation framework for RISC-V CPUs
☆174May 1, 2026Updated this week
Alternatives and similar repositories for difftest
Users that are interested in difftest are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Super fast RISC-V ISA emulator for XiangShan processor☆328Updated this week
- Open-source high-performance non-blocking cache☆95Apr 16, 2026Updated 2 weeks ago
- ☆14Jul 23, 2025Updated 9 months ago
- XiangShan Frontend Develop Environment☆71Updated this week
- Documentation for XiangShan☆435Apr 29, 2026Updated last week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆17Updated this week
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Sep 9, 2021Updated 4 years ago
- This repo includes XiangShan's function units☆30Apr 15, 2026Updated 3 weeks ago
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆31Feb 10, 2020Updated 6 years ago
- RISC-V SoC designed by students in UCAS☆1,525Apr 28, 2026Updated last week
- Open-source non-blocking L2 cache☆60Updated this week
- Artifact evaluation of paper: MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation☆50Apr 22, 2025Updated last year
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆34Apr 13, 2025Updated last year
- ☆15Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆25Mar 1, 2023Updated 3 years ago
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆68Updated this week
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆85Aug 29, 2023Updated 2 years ago
- The Scala parser to parse riscv/riscv-opcodes generate☆24Jan 21, 2026Updated 3 months ago
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆121Oct 31, 2024Updated last year
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 3 years ago
- The 'missing header' for Chisel☆23Feb 5, 2026Updated 3 months ago
- Simple RISC-V 3-stage Pipeline in Chisel☆607Aug 9, 2024Updated last year
- ☆71Feb 2, 2026Updated 3 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆29Mar 31, 2025Updated last year
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆896Updated this week
- Open-source high-performance RISC-V processor☆6,996Updated this week
- ☆314Updated this week
- A template project for beginning new Chisel work☆696Feb 24, 2026Updated 2 months ago
- 给NEMU移植Linux Kernel!☆22Jun 1, 2025Updated 11 months ago
- ☆95Apr 14, 2026Updated 3 weeks ago
- GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。☆27Dec 18, 2024Updated last year
- ☆141Updated this week
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Chisel/Firrtl execution engine☆157Aug 21, 2024Updated last year
- gem5 FS模式实验手册☆46Mar 8, 2023Updated 3 years ago
- nscscc2024，HPU河南理工大学参赛作品，两仪处理器☆11Aug 24, 2024Updated last year
- The Gee (寂) Operating System, written in YuLang.☆34Jun 28, 2021Updated 4 years ago
- Nix template for the chisel-based industrial designing flows.☆56Apr 23, 2025Updated last year
- chipyard in mill :P☆77Nov 20, 2023Updated 2 years ago
- NJU EMUlator, a full system x86/mips32/riscv32/riscv64 emulator for teaching☆1,110Nov 14, 2025Updated 5 months ago