Alternatives and similar repositories for difftest:

Users that are interested in difftest are comparing it to the libraries listed below

• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆152Updated 6 months ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆79Updated 2 weeks ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆50Updated 2 years ago
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆55Updated 2 weeks ago
• OpenXiangShan / GEM5
  ☆80Updated this week
• OSCPU / yosys-sta
  ☆63Updated this week
• OSCPU / chisel-playground
  ☆64Updated 2 months ago
• OSCPU / ysyxSoC
  ☆85Updated 2 months ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆52Updated 5 years ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆193Updated 3 weeks ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆67Updated 5 months ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆58Updated 3 years ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 8 months ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆46Updated this week
• OpenXiangShan / NEMU
  ☆272Updated this week
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆132Updated 2 years ago
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆179Updated 6 years ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆251Updated 2 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆41Updated 2 years ago
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆231Updated 8 months ago
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆68Updated last year
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆30Updated last week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆275Updated last year
• RV-BOSC / OpenNoC
  ☆144Updated 2 weeks ago
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆61Updated last year
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆193Updated last month
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆138Updated 2 months ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆82Updated 3 weeks ago
• riscv-ovpsim / imperas-riscv-tests
  ☆171Updated last year