Alternatives and similar repositories for difftest

Users that are interested in difftest are comparing it to the libraries listed below

• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆81Updated 3 weeks ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆156Updated 6 months ago
• OSCPU / yosys-sta
  ☆63Updated 3 weeks ago
• OSCPU / chisel-playground
  ☆67Updated 3 months ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆194Updated last month
• OSCPU / ysyxSoC
  ☆86Updated last week
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆67Updated 6 months ago
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆56Updated this week
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆58Updated 3 years ago
• OpenXiangShan / GEM5
  ☆84Updated this week
• OpenXiangShan / NEMU
  ☆274Updated this week
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆49Updated this week
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆83Updated last month
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆133Updated 2 years ago
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆179Updated 6 years ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆70Updated last year
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆250Updated 2 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆41Updated 3 years ago
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆78Updated last year
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated last month
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆279Updated last year
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆52Updated 5 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆194Updated 10 months ago
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆142Updated 3 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆149Updated last week
• RV-BOSC / OpenNoC
  ☆153Updated last week
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 9 months ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆150Updated 6 months ago