Alternatives and similar repositories for chisel-book

Users that are interested in chisel-book are comparing it to the libraries listed below

• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆741Updated 4 years ago
• chipsalliance / chisel-template
  A template project for beginning new Chisel work
  ☆683Updated 3 months ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,098Updated last year
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆603Updated last year
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆729Updated 4 months ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆749Updated last year
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,158Updated 7 months ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆918Updated 2 years ago
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆907Updated 4 years ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,169Updated 4 years ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆2,096Updated this week
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆758Updated 3 months ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,236Updated 3 months ago
• riscv-software-src / riscv-tests
  ☆1,107Updated this week
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆621Updated 3 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆694Updated 3 weeks ago
• eugene-tarassov / vivado-risc-v
  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
  ☆1,040Updated last month
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,369Updated last year
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,453Updated last month
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆632Updated 3 weeks ago
• riscv-non-isa / riscv-arch-test
  ☆628Updated this week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆557Updated 2 months ago
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆2,047Updated 2 weeks ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆693Updated last month
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆533Updated last year
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆636Updated this week
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,728Updated 3 weeks ago
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆414Updated 6 years ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆754Updated 2 months ago
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,903Updated this week