schoeberl / chisel-book
Digital Design with Chisel
☆811Updated last week
Alternatives and similar repositories for chisel-book:
Users that are interested in chisel-book are comparing it to the libraries listed below
- chisel tutorial exercises and answers☆713Updated 3 years ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,018Updated 6 months ago
- A template project for beginning new Chisel work☆624Updated last month
- Simple RISC-V 3-stage Pipeline in Chisel☆563Updated 7 months ago
- educational microarchitectures for risc-v isa☆704Updated this week
- Flexible Intermediate Representation for RTL☆738Updated 6 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,023Updated last month
- VeeR EH1 core☆858Updated last year
- 32-bit Superscalar RISC-V CPU☆956Updated 3 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,773Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,234Updated 2 weeks ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,487Updated 2 weeks ago
- RISC-V Formal Verification Framework☆596Updated 2 years ago
- Chisel examples and code snippets☆246Updated 2 years ago
- Random instruction generator for RISC-V processor verification☆1,074Updated last month
- Common SystemVerilog components☆583Updated 2 weeks ago
- Scala based HDL☆1,738Updated this week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆900Updated 3 months ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,839Updated this week
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆915Updated last week
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆646Updated 3 months ago
- SystemVerilog to Verilog conversion☆600Updated 2 weeks ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆479Updated 3 months ago
- ☆947Updated last week
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆403Updated last month
- Support for Rocket Chip on Zynq FPGAs☆406Updated 6 years ago
- OpenXuantie - OpenC910 Core☆1,235Updated 8 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆459Updated last month
- Functional verification project for the CORE-V family of RISC-V cores.☆503Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆558Updated this week