schoeberl / chisel-bookLinks
Digital Design with Chisel
☆842Updated last month
Alternatives and similar repositories for chisel-book
Users that are interested in chisel-book are comparing it to the libraries listed below
Sorting:
- chisel tutorial exercises and answers☆730Updated 3 years ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,042Updated 9 months ago
- A template project for beginning new Chisel work☆645Updated last month
- educational microarchitectures for risc-v isa☆715Updated 3 months ago
- Simple RISC-V 3-stage Pipeline in Chisel☆581Updated 10 months ago
- Flexible Intermediate Representation for RTL☆745Updated 10 months ago
- VeeR EH1 core☆883Updated 2 years ago
- Random instruction generator for RISC-V processor verification☆1,135Updated 2 weeks ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,080Updated 3 weeks ago
- 32-bit Superscalar RISC-V CPU☆1,036Updated 3 years ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,568Updated last week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,872Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,308Updated this week
- Chisel examples and code snippets☆254Updated 2 years ago
- Common SystemVerilog components☆627Updated this week
- The OpenPiton Platform☆710Updated last month
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆501Updated 4 months ago
- RISC-V Formal Verification Framework☆602Updated 3 years ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆918Updated 7 months ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆497Updated 6 months ago
- RISC-V Cores, SoC platforms and SoCs☆885Updated 4 years ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆435Updated this week
- SystemVerilog to Verilog conversion☆639Updated last month
- A Linux-capable RISC-V multicore for and by the world☆708Updated last month
- Working Draft of the RISC-V Debug Specification Standard☆487Updated last month
- OpenXuantie - OpenC910 Core☆1,281Updated 11 months ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,923Updated last month
- Functional verification project for the CORE-V family of RISC-V cores.☆556Updated 2 weeks ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆667Updated 3 weeks ago
- ☆567Updated this week