Alternatives and similar repositories for xfuzz

Users that are interested in xfuzz are comparing it to the libraries listed below

• iscas-tis / chisel-formal-verification
  Formal verification tools for Chisel and RISC-V
  ☆13Updated last year
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• iscas-tis / ChiRVFormal
  Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.
  ☆18Updated 8 months ago
• miaochenlu / Gem5_tutorials
  ☆22Updated 3 months ago
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆24Updated 8 months ago
• NSCSCC-2022-TJU / ChiselMIPS
  第六届龙芯杯混元形意太极门战队作品
  ☆18Updated 3 years ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆53Updated 5 years ago
• Seeker0472 / ysyx-linux
  给NEMU移植Linux Kernel!
  ☆22Updated 8 months ago
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆36Updated 4 years ago
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆35Updated last week
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆33Updated last year
• pku-liang / ksim
  ☆52Updated last year
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆33Updated last week
• lshpku / gem5-runahead
  Implementing the Precise Runahead (HPCA'20) in gem5
  ☆13Updated 2 years ago
• pku-liang / Hestia
  ☆17Updated 10 months ago
• CMU-SAFARI / Pythia-HDL
  Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …
  ☆17Updated 4 years ago
• OpenXiangShan / tl-test-new
  The Unified TileLink Memory Subsystem Tester for XiangShan
  ☆12Updated 3 weeks ago
• OpenXiangShan / gsim
  ☆65Updated last month
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆77Updated this week
• euphoric-hardware / rtl-simulation-reading
  ☆18Updated last month
• kuczmmar / Runahead
  Running ahead of memory latency - Part II project
  ☆10Updated 3 years ago
• OSCPU / archbench
  ☆11Updated last month
• observerw / ChiseLLM
  Reasoning LLMs optimized for Chisel code generation
  ☆23Updated 7 months ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆38Updated last year
• bu-icsg / ProcessorFuzz
  ☆14Updated last year
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆38Updated 3 years ago
• Kumonda221-CrO3 / gitlab-runner-vivado
  Vivado in GitLab-Runner for GitLab CI/CD
  ☆10Updated 3 years ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆28Updated 7 months ago
• comsec-group / encarsia
  ☆27Updated 10 months ago
• XS-MLVP / toffee
  A framework for building hardware verification platform using software method
  ☆32Updated last month