Fuzzing General-Purpose Hardware Designs with Software Fuzzers
☆24Jan 11, 2026Updated last month
Alternatives and similar repositories for xfuzz
Users that are interested in xfuzz are comparing it to the libraries listed below
Sorting:
- 给NEMU移植Linux Kernel!☆22Jun 1, 2025Updated 9 months ago
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 3 years ago
- Formal verification tools for Chisel and RISC-V☆13Jul 2, 2024Updated last year
- Dump Apple PMU counter definitions from `/usr/share/kpep` in macOS☆16Jan 8, 2026Updated last month
- 第六届龙芯杯混元形意太极门战队作品☆18May 15, 2022Updated 3 years ago
- ☆17Mar 17, 2022Updated 3 years ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆33Feb 20, 2024Updated 2 years ago
- Basic chisel difftest environment for RTL design (WIP☆20Mar 8, 2025Updated 11 months ago
- Xiangshan deterministic workloads generator☆24May 14, 2025Updated 9 months ago
- The Scala parser to parse riscv/riscv-opcodes generate☆24Jan 21, 2026Updated last month
- Microarchitecture diagrams of several CPUs☆46Feb 13, 2026Updated 2 weeks ago
- Learn NVDLA by SOMNIA☆42Dec 13, 2019Updated 6 years ago
- ☆22Nov 3, 2025Updated 3 months ago
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆25Nov 26, 2025Updated 3 months ago
- A Flexible Cache Architectural Simulator☆16Sep 16, 2025Updated 5 months ago
- ☆14Oct 30, 2024Updated last year
- ☆13May 8, 2025Updated 9 months ago
- Generate Linux Perf event tables for Apple Silicon☆17Dec 16, 2025Updated 2 months ago
- Running ahead of memory latency - Part II project☆10Jan 7, 2023Updated 3 years ago
- ☆11Dec 23, 2025Updated 2 months ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 10 months ago
- A docker image for One Student One Chip's debug exam☆10Sep 22, 2023Updated 2 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆33Feb 16, 2026Updated 2 weeks ago
- ☆78Oct 29, 2024Updated last year
- Nix template for the chisel-based industrial designing flows.☆52Apr 23, 2025Updated 10 months ago
- ☆13Feb 14, 2026Updated 2 weeks ago
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆18Feb 3, 2026Updated 3 weeks ago
- A suite of tools for pretty printing, diffing, and exploring abstract syntax trees.☆15Updated this week
- ☆14Sep 3, 2024Updated last year
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆36Jan 26, 2026Updated last month
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆119Oct 31, 2024Updated last year
- This is an IDE for YSYX_NPC debuging☆12Dec 10, 2024Updated last year
- Header-only C/C++ static keys to avoid the overhead of conditional branches☆14Feb 10, 2024Updated 2 years ago
- A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board.☆14Aug 7, 2022Updated 3 years ago
- 关于移植模型至gemmini的文档☆32May 4, 2022Updated 3 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Jul 23, 2022Updated 3 years ago
- jyy os enhanced☆13Jul 10, 2025Updated 7 months ago
- Fuzzing for SpinalHDL☆17Oct 10, 2022Updated 3 years ago