OpenXiangShan / xfuzz
Fuzzing General-Purpose Hardware Designs with Software Fuzzers
☆16Updated last month
Alternatives and similar repositories for xfuzz:
Users that are interested in xfuzz are comparing it to the libraries listed below
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆13Updated last month
- ☆17Updated 3 years ago
- A Modular Open-Source Hardware Fuzzing Framework☆32Updated 3 years ago
- ☆19Updated last year
- ☆18Updated 9 months ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆28Updated 2 months ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆18Updated this week
- Formal verification tools for Chisel and RISC-V☆14Updated 9 months ago
- Split large FIRRTL into separated modules for incremental compilation.☆10Updated 3 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆24Updated 6 months ago
- Code repository for Coppelia tool☆23Updated 4 years ago
- Project Repo for the Simulator Independent Coverage Research☆18Updated 2 years ago
- ☆33Updated 3 weeks ago
- The 'missing header' for Chisel☆19Updated 3 weeks ago
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆17Updated 5 months ago
- ☆12Updated 7 months ago
- Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…☆12Updated last month
- ☆22Updated 2 years ago
- Xiangshan deterministic workloads generator☆17Updated last month
- Run Rocket Chip on VCU128☆30Updated 4 months ago
- A Flexible Cache Architectural Simulator☆14Updated 4 months ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆30Updated this week
- ☆17Updated 10 months ago
- 给NEMU移植Linux Kernel!☆14Updated 3 weeks ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆31Updated last year
- ☆27Updated this week
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆19Updated last year
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆52Updated 5 years ago
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆27Updated 5 years ago