OpenXiangShan / xfuzz
Fuzzing General-Purpose Hardware Designs with Software Fuzzers
☆16Updated this week
Alternatives and similar repositories for xfuzz:
Users that are interested in xfuzz are comparing it to the libraries listed below
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆13Updated 3 weeks ago
- ☆17Updated 3 years ago
- Xiangshan deterministic workloads generator☆18Updated 2 months ago
- A Modular Open-Source Hardware Fuzzing Framework☆33Updated 3 years ago
- ☆19Updated last year
- Project Repo for the Simulator Independent Coverage Research☆19Updated 2 years ago
- Formal verification tools for Chisel and RISC-V☆13Updated 10 months ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆28Updated 2 months ago
- ☆19Updated 9 months ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆18Updated last week
- ☆12Updated 8 months ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆31Updated last year
- 本项目已被合并至官方Chiplab中☆12Updated 3 months ago
- Code repository for Coppelia tool☆23Updated 4 years ago
- Run Rocket Chip on VCU128☆30Updated 5 months ago
- ☆12Updated 10 months ago
- ☆18Updated 5 years ago
- Split large FIRRTL into separated modules for incremental compilation.☆10Updated 3 years ago
- Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…☆12Updated 2 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly☆15Updated 3 years ago
- ☆18Updated 10 months ago
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆25Updated 7 months ago
- CleanupSpec (MICRO-2019)☆17Updated 4 years ago
- ☆33Updated last month
- This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…☆17Updated 2 years ago
- The 'missing header' for Chisel☆20Updated last month
- A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…☆20Updated 10 months ago
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆52Updated 5 years ago
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆19Updated last year