Alternatives and similar repositories for xfuzz:

Users that are interested in xfuzz are comparing it to the libraries listed below

• iscas-tis / riscv-spec-core
  Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.
  ☆12Updated 2 weeks ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆32Updated 3 years ago
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆27Updated last month
• miaochenlu / Gem5_tutorials
  ☆18Updated last year
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆29Updated 4 months ago
• iscas-tis / CHA
  ☆17Updated 8 months ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆18Updated last week
• iscas-tis / chisel-formal-verification
  Formal verification tools for Chisel and RISC-V
  ☆14Updated 8 months ago
• bu-icsg / ProcessorFuzz
  ☆12Updated 6 months ago
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆31Updated last year
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆17Updated 3 weeks ago
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆18Updated last week
• CMU-SAFARI / Load-Inspector
  A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…
  ☆20Updated 8 months ago
• lizhirui / DreamCoreV2
  ☆22Updated last year
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• sequencer / arithmetic
  ☆32Updated last week
• Jpz-sdju / trinity
  ☆19Updated 2 weeks ago
• MaxXSoft / Frenda
  Split large FIRRTL into separated modules for incremental compilation.
  ☆10Updated 3 years ago
• pku-liang / hestia
  ☆12Updated this week
• epfl-vlsc / parendi
  Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU
  ☆19Updated 11 months ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆30Updated 11 months ago
• pku-liang / ksim
  ☆40Updated 2 months ago
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆26Updated 5 years ago
• ekiwi / simulator-independent-coverage
  Project Repo for the Simulator Independent Coverage Research
  ☆18Updated 2 years ago
• wshenyi / EECS-470-FinalProject
  A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.
  ☆14Updated 2 years ago
• rzhang2285 / Coppelia
  Code repository for Coppelia tool
  ☆23Updated 4 years ago
• lshpku / gem5-runahead
  Implementing the Precise Runahead (HPCA'20) in gem5
  ☆11Updated last year
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆15Updated 3 years ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆52Updated 4 years ago