whutddk / Rift2CoreLinks
Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
☆40Updated last year
Alternatives and similar repositories for Rift2Core
Users that are interested in Rift2Core are comparing it to the libraries listed below
Sorting:
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 9 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆69Updated last year
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆30Updated 4 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 5 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- The official NaplesPU hardware code repository☆17Updated 6 years ago
- ☆71Updated this week
- For contributions of Chisel IP to the chisel community.☆64Updated 9 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆63Updated 6 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated 9 months ago
- ☆32Updated last week
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆19Updated 2 months ago
- DDR4 Simulation Project in System Verilog☆42Updated 10 years ago
- ☆33Updated 4 months ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆48Updated 4 years ago
- Open-source high-performance non-blocking cache☆87Updated 2 months ago
- The multi-core cluster of a PULP system.☆105Updated last week
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated 2 months ago
- Synthesisable SIMT-style RISC-V GPGPU☆40Updated 3 weeks ago
- PCI Express controller model☆60Updated 2 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆56Updated last year
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆41Updated last year
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆28Updated 5 years ago
- Hardware design with Chisel☆34Updated 2 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆45Updated 3 years ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆59Updated 8 months ago