whutddk / Rift2CoreLinks
Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
☆40Updated last year
Alternatives and similar repositories for Rift2Core
Users that are interested in Rift2Core are comparing it to the libraries listed below
Sorting:
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆30Updated 4 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 5 years ago
- Simple runtime for Pulp platforms☆48Updated this week
- ☆23Updated 7 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆62Updated 5 months ago
- Chisel Things for OFDM☆32Updated 5 years ago
- For contributions of Chisel IP to the chisel community.☆64Updated 8 months ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆48Updated 4 years ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆69Updated 11 months ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- ☆31Updated last week
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated 2 months ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 2 months ago
- Advanced Debug Interface☆15Updated 5 months ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆49Updated 8 months ago
- Hamming ECC Encoder and Decoder to protect memories☆33Updated 5 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆36Updated last year
- DDR4 Simulation Project in System Verilog☆41Updated 10 years ago
- ☆30Updated this week
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Updated last year
- ☆68Updated this week
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆37Updated 3 weeks ago
- PCI Express controller model☆58Updated 2 years ago