whutddk / Rift2CoreLinks
Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
☆40Updated last year
Alternatives and similar repositories for Rift2Core
Users that are interested in Rift2Core are comparing it to the libraries listed below
Sorting:
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆43Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 10 months ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆30Updated 4 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆49Updated 4 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 5 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- RV64GC Linux Capable RISC-V Core☆33Updated last month
- The official NaplesPU hardware code repository☆18Updated 6 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- ☆73Updated last week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆65Updated 7 months ago
- For contributions of Chisel IP to the chisel community.☆65Updated 10 months ago
- ☆32Updated last week
- Setup scripts and files needed to compile CoreMark on RISC-V☆70Updated last year
- PCI Express controller model☆65Updated 2 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated 10 months ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated 2 weeks ago
- Hardware design with Chisel☆34Updated 2 years ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆18Updated 7 years ago
- Synthesisable SIMT-style RISC-V GPGPU☆40Updated 2 months ago
- DDR4 Simulation Project in System Verilog☆41Updated 11 years ago
- The multi-core cluster of a PULP system.☆108Updated this week
- ☆33Updated 5 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- RISC-V IOMMU in verilog☆19Updated 3 years ago
- RISC-V Nexus Trace TG documentation and reference code☆52Updated 8 months ago
- Chisel Things for OFDM☆32Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 7 months ago
- Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.☆32Updated 5 years ago