A riscv emulator.
☆19Feb 5, 2024Updated 2 years ago
Alternatives and similar repositories for Yuri
Users that are interested in Yuri are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The Scala parser to parse riscv/riscv-opcodes generate☆25Jan 21, 2026Updated 2 months ago
- This is an IDE for YSYX_NPC debuging☆12Dec 10, 2024Updated last year
- Koishi VTuberized Logo☆11Oct 19, 2024Updated last year
- A RISC-V core running Debian (and a LoongArch core running Linux).☆23Nov 24, 2025Updated 4 months ago
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆25Mar 8, 2026Updated 2 weeks ago
- Unofficial guide for ysyx students applying to ShanghaiTech University☆23Feb 25, 2025Updated last year
- 本项目已被合并至官方Chiplab中☆13Jan 13, 2025Updated last year
- A curated list of awesome things related to Satori☆12Oct 16, 2024Updated last year
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆26Jan 2, 2025Updated last year
- RISC-V 64 CPU☆10Oct 4, 2025Updated 5 months ago
- ☆11Dec 23, 2025Updated 3 months ago
- A hand-written recursive decent Verilog parser.☆10Jan 30, 2026Updated last month
- 适用于龙芯杯团队赛入门选手的应急cache模块☆32Mar 13, 2024Updated 2 years ago
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆18Sep 29, 2024Updated last year
- ☆30Jan 23, 2025Updated last year
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆67Updated this week
- Basic chisel difftest environment for RTL design (WIP☆20Mar 8, 2025Updated last year
- Second Prize in NSCSCC 2024. An out-of-order CPU designed by NoAXI team from HDU. 2024年全国大学生计算机系统能力大赛CPU设计赛(龙芯杯)团队赛二等奖作品☆23Sep 14, 2024Updated last year
- 给NEMU移植Linux Kernel!☆22Jun 1, 2025Updated 9 months ago
- Tiny Tapeout GDS Action (using OpenLane)☆20Mar 16, 2026Updated last week
- ☆67Mar 3, 2026Updated 2 weeks ago
- Dump Apple PMU counter definitions from `/usr/share/kpep` in macOS☆16Mar 6, 2026Updated 2 weeks ago
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆121Oct 31, 2024Updated last year
- Wireguard, but compatible with mpls, no MTU overhead☆17Jan 7, 2025Updated last year
- A docker image for One Student One Chip's debug exam☆10Sep 22, 2023Updated 2 years ago
- 5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany☆13Dec 4, 2025Updated 3 months ago
- 顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel☆26Jan 25, 2026Updated last month
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 3 years ago
- ☆14Oct 30, 2024Updated last year
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Dec 31, 2018Updated 7 years ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆202Oct 14, 2024Updated last year
- HITSZ 404 NOT FOUND NSCSCC22 project☆15Sep 8, 2022Updated 3 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Jul 23, 2022Updated 3 years ago
- ☆13Mar 15, 2026Updated last week
- ☆36Jul 22, 2025Updated 8 months ago
- tldr file for riscv assembly instructions☆18Feb 28, 2021Updated 5 years ago
- (梗)Meme.☆14Apr 2, 2024Updated last year
- Generate Linux Perf event tables for Apple Silicon☆17Dec 16, 2025Updated 3 months ago
- DUTH RISC-V Superscalar Microprocessor☆34Oct 23, 2024Updated last year