Anillc / YuriLinks
A riscv emulator.
☆19Updated last year
Alternatives and similar repositories for Yuri
Users that are interested in Yuri are comparing it to the libraries listed below
Sorting:
- Nix template for the chisel-based industrial designing flows.☆45Updated 5 months ago
- The Scala parser to parse riscv/riscv-opcodes generate☆21Updated last month
- Unofficial guide for ysyx students applying to ShanghaiTech University☆22Updated 7 months ago
- 本项目已被合并至官方Chiplab中☆12Updated 8 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- Open-source RISC-V cryptographic hardware token, RTL repo☆19Updated 2 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- 给NEMU移植Linux Kernel!☆20Updated 4 months ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated last week
- Vivado in GitLab-Runner for GitLab CI/CD☆10Updated 2 years ago
- ☆55Updated 3 weeks ago
- This is an IDE for YSYX_NPC debuging☆12Updated 9 months ago
- ☆11Updated 7 months ago
- ☆30Updated 8 months ago
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆118Updated 11 months ago
- The 'missing header' for Chisel☆21Updated 6 months ago
- Basic chisel difftest environment for RTL design (WIP☆18Updated 6 months ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆44Updated last year
- Formal verification tools for Chisel and RISC-V☆13Updated last year
- VSH(SHell for Visualizing vcd file)项目为数字波形文件命令行查看器。☆24Updated last month
- Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.☆31Updated last year
- CQU Dual Issue Machine☆37Updated last year
- nscscc2024,HPU河南理工大学参赛作品,两仪处理器☆11Updated last year
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated 5 months ago
- Second Prize in NSCSCC 2024. Out-of-order CPU design from HDU. 2024年全国大学生计算机系统能力大赛CPU设计赛(龙芯杯)团队赛二等奖作品☆20Updated last year
- Wrappers for open source FPU hardware implementations.☆34Updated last year
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆18Updated 9 months ago
- Xiangshan deterministic workloads generator☆20Updated 4 months ago
- My RV64 CPU (Work in progress)☆19Updated 2 years ago
- Summary of bugs in Xuantie C9XX core design. include C906/C908/C910/C920☆24Updated 2 months ago