chipsalliance / rvdecoderdb
The Scala parser to parse riscv/riscv-opcodes generate
☆19Updated this week
Alternatives and similar repositories for rvdecoderdb:
Users that are interested in rvdecoderdb are comparing it to the libraries listed below
- Basic chisel difftest environment for RTL design (WIP☆18Updated last month
- Unofficial guide for ysyx students applying to ShanghaiTech University☆21Updated 2 months ago
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆16Updated 3 months ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated last week
- This is an IDE for YSYX_NPC debuging☆12Updated 4 months ago
- Build mini linux for your own RISC-V emulator!☆19Updated 7 months ago
- "aura" my super-scalar O3 cpu core☆24Updated 11 months ago
- Second Prize in NSCSCC 2024. Developed by team NoAXI from Hangzhou Dianzi University.☆16Updated 7 months ago
- Documentation for XiangShan Design☆23Updated this week
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated last year
- ☆11Updated 2 months ago
- 本项目已被合并至官方Chiplab中☆11Updated 3 months ago
- ☆27Updated this week
- ☆66Updated 8 months ago
- Nix template for the chisel-based industrial designing flows.☆41Updated this week
- ☆22Updated 2 weeks ago
- 给NEMU移植Linux Kernel!☆14Updated last month
- NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.☆11Updated 3 weeks ago
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆32Updated this week
- ☆17Updated last month
- Pick your favorite language to verify your chip.☆47Updated this week
- 顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel☆19Updated 5 months ago
- ☆63Updated this week
- ☆21Updated 3 weeks ago
- VSH（SHell for Visualizing vcd file）项目为数字波形文件命令行查看器。☆19Updated this week
- The official website of One Student One Chip project.☆10Updated last week
- ☆85Updated 2 months ago
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆16Updated 6 months ago
- Xiangshan deterministic workloads generator☆17Updated last month