freechipsproject / ip-contributionsLinks
For contributions of Chisel IP to the chisel community.
☆68Updated last year
Alternatives and similar repositories for ip-contributions
Users that are interested in ip-contributions are comparing it to the libraries listed below
Sorting:
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- Chisel Cheatsheet☆34Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- ☆88Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 4 months ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated last year
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆51Updated last year
- The specification for the FIRRTL language☆62Updated last week
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- The multi-core cluster of a PULP system.☆109Updated last month
- Generic Register Interface (contains various adapters)☆133Updated 2 weeks ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43Updated 2 years ago
- A RISC-V Core (RV32I) written in Chisel HDL☆104Updated 2 weeks ago
- pulp_soc is the core building component of PULP based SoCs☆81Updated 8 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆70Updated last week
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆116Updated last year
- Chisel components for FPGA projects☆127Updated 2 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆113Updated 2 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆43Updated 2 years ago
- Lipsi: Probably the Smallest Processor in the World☆88Updated last year
- An implementation of RISC-V☆44Updated 2 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆189Updated 2 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆89Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago