freechipsproject / ip-contributionsLinks
For contributions of Chisel IP to the chisel community.
☆67Updated last year
Alternatives and similar repositories for ip-contributions
Users that are interested in ip-contributions are comparing it to the libraries listed below
Sorting:
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 weeks ago
- Chisel Cheatsheet☆34Updated 2 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated last year
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 4 months ago
- ☆87Updated this week
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- Chisel components for FPGA projects☆127Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆122Updated 4 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆116Updated 4 years ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43Updated 2 years ago
- Generic Register Interface (contains various adapters)☆133Updated last month
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 10 years ago
- pulp_soc is the core building component of PULP based SoCs☆81Updated 8 months ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- The specification for the FIRRTL language☆62Updated last week
- Lipsi: Probably the Smallest Processor in the World☆88Updated last year
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated last year
- The multi-core cluster of a PULP system.☆109Updated 2 weeks ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆112Updated 2 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- RISC-V Nox core☆68Updated 3 months ago
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆91Updated 10 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated last month
- SpinalHDL Hardware Math Library☆93Updated last year
- Provides dot visualizations of chisel/firrtl circuits☆122Updated 2 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆115Updated last year