freechipsproject / ip-contributions
For contributions of Chisel IP to the chisel community.
☆59Updated 4 months ago
Alternatives and similar repositories for ip-contributions:
Users that are interested in ip-contributions are comparing it to the libraries listed below
- Chisel Cheatsheet☆33Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 6 months ago
- A caravan equipped with API for creating bus protocols in Chisel with ease.☆14Updated 3 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆37Updated 2 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆59Updated last year
- pulp_soc is the core building component of PULP based SoCs☆79Updated last week
- Open source high performance IEEE-754 floating unit☆67Updated last year
- Hardware generator debugger☆73Updated last year
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆44Updated 4 months ago
- A SystemVerilog source file pickler.☆55Updated 4 months ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- Generic Register Interface (contains various adapters)☆111Updated 5 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆66Updated last week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆48Updated last month
- ☆32Updated last month
- (System)Verilog to Chisel translator☆111Updated 2 years ago
- Tests for example Rocket Custom Coprocessors☆72Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Platform Level Interrupt Controller☆36Updated 10 months ago
- Re-coded Xilinx primitives for Verilator use☆43Updated last year
- The multi-core cluster of a PULP system.☆85Updated last week
- ☆88Updated last year
- Examples for creating AXI-interfaced peripherals in Chisel☆74Updated 9 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆80Updated last week
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- ☆53Updated 4 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆50Updated 3 years ago