OSCC-Project / iEDALinks
☆377Updated this week
Alternatives and similar repositories for iEDA
Users that are interested in iEDA are comparing it to the libraries listed below
Sorting:
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆145Updated last month
- OpenSTA engine☆471Updated this week
- EDA wiki☆127Updated 2 months ago
- CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA)☆371Updated 3 weeks ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆254Updated 3 months ago
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆432Updated this week
- A High-performance Timing Analysis Tool for VLSI Systems☆624Updated 2 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆177Updated 5 years ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆168Updated 2 weeks ago
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆331Updated last week
- ☆268Updated 4 years ago
- ☆166Updated 2 months ago
- EPFL logic synthesis benchmarks☆192Updated 2 weeks ago
- ☆159Updated last month
- ☆146Updated 3 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆500Updated 3 months ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆212Updated 7 months ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆201Updated this week
- Common SystemVerilog components☆626Updated this week
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆292Updated 3 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆393Updated last week
- Deep learning toolkit-enabled VLSI placement☆815Updated last month
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆136Updated last year
- ☆300Updated 2 months ago
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆122Updated last week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆282Updated 3 weeks ago
- This repo awesome-AI4EDA contains the source for the webpage: https://ai4eda.github.io, which is a curated paper list of awesome AI for E…☆149Updated 11 months ago
- SystemVerilog to Verilog conversion☆631Updated 2 weeks ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆136Updated 2 years ago
- IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow …☆178Updated 5 months ago