riscv-stc / riscv-matrix-spec
RISC-V Matrix Specification
☆15Updated 2 months ago
Related projects ⓘ
Alternatives and complementary repositories for riscv-matrix-spec
- ☆37Updated 5 years ago
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆23Updated 7 months ago
- Unit tests generator for RVV 1.0☆62Updated last month
- Setup scripts and files needed to compile CoreMark on RISC-V☆64Updated 4 months ago
- HLS for Networks-on-Chip☆31Updated 3 years ago
- Tests for example Rocket Custom Coprocessors☆69Updated 4 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆93Updated this week
- Pure digital components of a UCIe controller☆48Updated 2 weeks ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆75Updated this week
- Chisel RISC-V Vector 1.0 Implementation☆54Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆59Updated this week
- ☆15Updated 3 months ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆24Updated last month
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆46Updated 7 years ago
- Advanced Architecture Labs with CVA6☆49Updated 10 months ago
- DUTH RISC-V Superscalar Microprocessor☆28Updated 3 weeks ago
- ☆75Updated 2 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆109Updated 3 weeks ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆57Updated last year
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆85Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆48Updated 5 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆47Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- Original test vector of RISC-V Vector Extension☆11Updated 3 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆22Updated last month
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆95Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 7 months ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆32Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆106Updated 3 years ago
- This is the fork of CVA6 intended for PULP development.☆16Updated last week