riscv-stc / riscv-matrix-specLinks
RISC-V Matrix Specification
☆22Updated 6 months ago
Alternatives and similar repositories for riscv-matrix-spec
Users that are interested in riscv-matrix-spec are comparing it to the libraries listed below
Sorting:
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆30Updated last year
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆28Updated this week
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆33Updated last week
- HLS for Networks-on-Chip☆35Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆46Updated 8 months ago
- matrix-coprocessor for RISC-V☆18Updated 2 months ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆37Updated last week
- ☆65Updated last week
- upstream: https://github.com/RALC88/gem5☆31Updated 2 years ago
- SystemC training aimed at TLM.☆30Updated 4 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆105Updated last year
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆57Updated this week
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- ☆50Updated 6 years ago
- Unit tests generator for RVV 1.0☆88Updated last month
- The official NaplesPU hardware code repository☆16Updated 5 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆148Updated 4 months ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- Advanced Architecture Labs with CVA6☆62Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆84Updated this week
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- Input / Output Physical Memory Protection Unit for RISC-V☆12Updated last year
- Setup scripts and files needed to compile CoreMark on RISC-V☆68Updated 11 months ago
- The gem5-X open source framework (based on the gem5 simulator)☆41Updated 2 years ago
- Development of a Network on Chip Simulation using SystemC.☆33Updated 7 years ago
- ☆47Updated 2 months ago