RISC-V Matrix Specification
☆26Dec 2, 2024Updated last year
Alternatives and similar repositories for riscv-matrix-spec
Users that are interested in riscv-matrix-spec are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆38Mar 26, 2024Updated 2 years ago
- Administrative repository for the Attached Matrix Facility Task Group☆14Dec 11, 2023Updated 2 years ago
- A matrix extension proposal for AI applications under RISC-V architecture☆183Apr 1, 2026Updated 2 months ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆251May 29, 2026Updated last week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆12May 29, 2026Updated last week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆17Jun 2, 2026Updated last week
- A Goldschmidt integer divider written in verilog. Similar to Newton-Raphson but the divison step can be pipelined.☆16Apr 25, 2024Updated 2 years ago
- RISC-V Rocket on the Digilent Zybo Board☆21Aug 6, 2014Updated 11 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- Open-source non-blocking L2 cache☆62Updated this week
- ordspecsim: The Swarm architecture simulator☆25Feb 15, 2023Updated 3 years ago
- SCARV: a side-channel hardened RISC-V platform☆28Jan 11, 2023Updated 3 years ago
- ☆318May 13, 2026Updated 3 weeks ago
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated 2 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆50Jan 31, 2022Updated 4 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆166Jan 25, 2024Updated 2 years ago
- ☆12Feb 15, 2024Updated 2 years ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆56Jan 20, 2026Updated 4 months ago
- ☆39Mar 6, 2026Updated 3 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆158Updated this week
- ☆19Jan 2, 2026Updated 5 months ago
- RISCV C and Triton AI-Benchmark☆25Jan 28, 2026Updated 4 months ago
- ☆107May 15, 2026Updated 3 weeks ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- A risc v based architecture to develop a core/ processor which is capable of Matrix MAC Operations☆12May 31, 2026Updated last week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆524Jun 2, 2026Updated last week
- ☆14Dec 15, 2022Updated 3 years ago
- A hand-written recursive decent Verilog parser.☆10May 7, 2026Updated last month
- Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.☆26Jun 7, 2021Updated 5 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆23Nov 24, 2025Updated 6 months ago
- The ISA specification for the ZiCondOps extension.☆19Mar 21, 2024Updated 2 years ago
- A small RISC-V kernel coding by C, tested on sifive unmatched board.☆16Aug 20, 2022Updated 3 years ago
- ☆376Jun 1, 2026Updated last week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Lab assignments for the Agile Hardware Design course☆19Nov 14, 2025Updated 6 months ago
- A formalization of the RVWMO (RISC-V) memory model☆37Jun 23, 2022Updated 3 years ago
- Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.☆20Jul 29, 2021Updated 4 years ago
- example using the httpapi connection plugin☆11Sep 19, 2018Updated 7 years ago
- Modified version of PULP Ara to support Vector Cryptography (Zvk) Instructions☆18Jan 21, 2026Updated 4 months ago
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆20May 20, 2026Updated 2 weeks ago
- Computer architecture learning environment using FPGAs☆15May 17, 2021Updated 5 years ago