RISMicroDevices / CHIronLinks
Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
☆33Updated last week
Alternatives and similar repositories for CHIron
Users that are interested in CHIron are comparing it to the libraries listed below
Sorting:
- DUTH RISC-V Superscalar Microprocessor☆33Updated last year
- ☆22Updated 2 years ago
- The official NaplesPU hardware code repository☆21Updated 6 years ago
- Advanced Architecture Labs with CVA6☆73Updated 2 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆48Updated last month
- A Heterogeneous GPU Platform for Chipyard SoC☆42Updated this week
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆19Updated 9 months ago
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆34Updated 3 months ago
- ☆33Updated 10 months ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆31Updated last month
- ☆33Updated 2 months ago
- SystemVerilog implemention of the TAGE branch predictor☆13Updated 4 years ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆23Updated this week
- ☆20Updated last month
- ☆32Updated 6 months ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆20Updated 9 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Updated 4 years ago
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆17Updated last year
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆23Updated 10 months ago
- ☆58Updated 6 years ago
- An almost empty chisel project as a starting point for hardware design☆33Updated last year
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- AIA IP compliant with the RISC-V AIA spec☆46Updated last year
- ☆23Updated this week
- RISC-V Matrix Specification☆23Updated last year
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆46Updated last week
- The RTL source for AnyCore RISC-V☆33Updated 3 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆46Updated 2 years ago