RISMicroDevices / CHIronLinks
Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
☆19Updated 2 months ago
Alternatives and similar repositories for CHIron
Users that are interested in CHIron are comparing it to the libraries listed below
Sorting:
- DUTH RISC-V Superscalar Microprocessor☆31Updated 9 months ago
- The official NaplesPU hardware code repository☆17Updated 6 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆19Updated 2 months ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆28Updated last week
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- ☆22Updated 2 years ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆36Updated 7 months ago
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆27Updated last week
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆16Updated last month
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆38Updated last month
- ☆16Updated this week
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆34Updated 7 months ago
- ☆30Updated last week
- SystemVerilog implemention of the TAGE branch predictor☆12Updated 4 years ago
- ☆33Updated 4 months ago
- Original test vector of RISC-V Vector Extension☆14Updated 4 years ago
- RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm☆24Updated last month
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆36Updated last month
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆17Updated 3 months ago
- ☆29Updated 4 years ago
- RISC-V IOMMU in verilog☆17Updated 3 years ago
- Advanced Architecture Labs with CVA6☆65Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- ☆44Updated 6 months ago
- RISC-V Matrix Specification☆22Updated 8 months ago
- ☆20Updated 4 months ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated 2 months ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆14Updated this week