Alternatives and similar repositories for gsim

Users that are interested in gsim are comparing it to the libraries listed below

• OpenXiangShan / XiangShan-Design-Doc
  Documentation for XiangShan Design
  ☆29Updated this week
• OSCPU / openperf
  ☆11Updated 5 months ago
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆19Updated 2 months ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 3 months ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆51Updated last week
• puckbee / moli
  ☆15Updated last week
• Kumonda221-CrO3 / gitlab-runner-vivado
  Vivado in GitLab-Runner for GitLab CI/CD
  ☆10Updated 2 years ago
• OSCPU / chisel-playground
  ☆67Updated 5 months ago
• JamesAslan / MicroArchBench
  ☆73Updated 8 months ago
• ftppz / ShanghaiTech-YSYX
  Unofficial guide for ysyx students applying to ShanghaiTech University
  ☆22Updated 4 months ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆35Updated last year
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 11 months ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated 8 months ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• OSCPU / yosys-sta
  ☆73Updated 3 months ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆147Updated this week
• oscc-web / ysyx-website
  The official website of One Student One Chip project.
  ☆10Updated last week
• arch-simulator-sig / chisel-env
  Basic chisel difftest environment for RTL design (WIP
  ☆18Updated 4 months ago
• Seeker0472 / ysyx-linux
  给NEMU移植Linux Kernel!
  ☆18Updated last month
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆81Updated last year
• OpenXiangShan / GEM5
  ☆90Updated this week
• NoAXI / NoAXI-LoongArch-CPU
  Second Prize in NSCSCC 2024. Developed by team NoAXI from Hangzhou Dianzi University.
  ☆17Updated 10 months ago
• CmdBlockZQG / rvcore-mini-linux
  Build mini linux for your own RISC-V emulator!
  ☆21Updated 10 months ago
• OSCPU / ysyxSoC
  ☆86Updated 2 months ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆172Updated 9 months ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆68Updated 8 months ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆49Updated last year
• Jpz-sdju / trinity
  ☆24Updated 3 months ago
• Siudya / Nanhu
  Open-source high-performance RISC-V processor
  ☆28Updated last month