☆67Updated this week
Alternatives and similar repositories for gsim
Users that are interested in gsim are comparing it to the libraries listed below
Sorting:
- ☆11Dec 23, 2025Updated 2 months ago
- This is an IDE for YSYX_NPC debuging☆12Dec 10, 2024Updated last year
- The 'missing header' for Chisel☆23Feb 5, 2026Updated 3 weeks ago
- ☆52Jan 16, 2025Updated last year
- Unofficial guide for ysyx students applying to ShanghaiTech University☆23Feb 25, 2025Updated last year
- Nix template for the chisel-based industrial designing flows.☆52Apr 23, 2025Updated 10 months ago
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- Basic chisel difftest environment for RTL design (WIP☆20Mar 8, 2025Updated 11 months ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆36Jan 26, 2026Updated last month
- A fork of Xiangshan for AI☆36Feb 6, 2026Updated 3 weeks ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Nov 24, 2025Updated 3 months ago
- ☆78Oct 29, 2024Updated last year
- ☆22Apr 16, 2023Updated 2 years ago
- nscscc2024，HPU河南理工大学参赛作品，两仪处理器☆11Aug 24, 2024Updated last year
- CPU敏捷开发框架（龙芯杯2024）☆25Sep 6, 2024Updated last year
- 顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel☆25Jan 25, 2026Updated last month
- 无刷电机驱动 程序+电路板 FOC for BLDC motor, code and PCB project☆14Jan 27, 2024Updated 2 years ago
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 3 years ago
- SUSTech CS202 (Computer Organization) Project, with CPU hardware implemented in Chisel(Scala) and software cross-compiled from Rust.☆34Jun 16, 2023Updated 2 years ago
- VSH（SHell for Visualizing vcd file）项目为数字波形文件命令行查看器。☆25Dec 8, 2025Updated 2 months ago
- high-performance RTL simulator☆186Jun 19, 2024Updated last year
- The official website of One Student One Chip project.☆11Feb 5, 2026Updated 3 weeks ago
- 本项目已被合并至官方Chiplab中☆13Jan 13, 2025Updated last year
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆65Feb 22, 2026Updated last week
- ☆42Dec 5, 2025Updated 2 months ago
- ☆30Jan 23, 2025Updated last year
- ☆93Sep 30, 2025Updated 5 months ago
- ☆66Aug 5, 2024Updated last year
- Pick your favorite language to verify your chip.☆77Jan 30, 2026Updated last month
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆24Jan 11, 2026Updated last month
- ☆17Mar 17, 2022Updated 3 years ago
- 给NEMU移植Linux Kernel!☆22Jun 1, 2025Updated 9 months ago
- ☆21May 26, 2025Updated 9 months ago
- Documentation for XiangShan Design☆42Feb 3, 2026Updated 3 weeks ago
- The Scala parser to parse riscv/riscv-opcodes generate☆24Jan 21, 2026Updated last month
- Xiangshan deterministic workloads generator☆24May 14, 2025Updated 9 months ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆22May 12, 2025Updated 9 months ago
- How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design☆626Aug 13, 2024Updated last year
- Examine and discover LoongArch instructions☆22Jul 11, 2025Updated 7 months ago