☆33Mar 20, 2025Updated last year
Alternatives and similar repositories for arithmetic
Users that are interested in arithmetic are comparing it to the libraries listed below
Sorting:
- The 'missing header' for Chisel☆24Feb 5, 2026Updated last month
- ☆12May 20, 2021Updated 4 years ago
- chipyard in mill :P☆77Nov 20, 2023Updated 2 years ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆233Aug 19, 2024Updated last year
- ☆19Jul 12, 2024Updated last year
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Feb 17, 2022Updated 4 years ago
- ☆14Aug 31, 2025Updated 6 months ago
- The working draft to split rocket core out from rocket chip☆14Dec 22, 2023Updated 2 years ago
- ☆20Mar 3, 2026Updated 2 weeks ago
- ☆11Dec 23, 2025Updated 2 months ago
- MIPS R10000 architecture simulator with C++☆10Jun 8, 2023Updated 2 years ago
- Example of Chisel3 Diplomacy☆11Feb 23, 2022Updated 4 years ago
- For contributions of Chisel IP to the chisel community.☆71Nov 7, 2024Updated last year
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆19Mar 4, 2026Updated 2 weeks ago
- LTE/WiFi/5G-NR SDR Transceiver☆56Dec 18, 2018Updated 7 years ago
- high-performance RTL simulator☆188Jun 19, 2024Updated last year
- Open-source RISC-V cryptographic hardware token, RTL repo☆20Nov 9, 2022Updated 3 years ago
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆12May 24, 2019Updated 6 years ago
- Python script for controlling the debug-jtag port of riscv cores☆15Mar 27, 2021Updated 4 years ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 3 months ago
- Chisel/Firrtl execution engine☆155Aug 21, 2024Updated last year
- Summary of bugs in Xuantie C9XX core design. include C906/C908/C910/C920☆29Feb 10, 2026Updated last month
- Equivalence checking with Yosys☆58Mar 4, 2026Updated 2 weeks ago
- A dynamic verification library for Chisel.☆160Nov 9, 2024Updated last year
- ☆312Updated this week
- Miscellaneous components for bluespec☆11Nov 18, 2024Updated last year
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Feb 1, 2020Updated 6 years ago
- Loongarch Emulator☆19Mar 14, 2025Updated last year
- ☆81Oct 29, 2024Updated last year
- Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer.☆18Feb 26, 2023Updated 3 years ago
- (System)Verilog to Chisel translator☆116May 20, 2022Updated 3 years ago
- An out-of-order processor that supports multiple instruction sets.☆21Aug 23, 2022Updated 3 years ago
- Open source high performance IEEE-754 floating unit☆91Feb 26, 2024Updated 2 years ago
- Cryptography accelerator ASIC (for AES128/AES256 and SHA256) using Skywater 130nm process node (main project repo). Taped out in December…☆23Jan 13, 2021Updated 5 years ago
- ☆10Jan 25, 2023Updated 3 years ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Sep 9, 2021Updated 4 years ago
- ☆10Oct 15, 2021Updated 4 years ago
- Chisel examples and code snippets☆271Aug 1, 2022Updated 3 years ago