sequencer / arithmetic

Related projects ⓘ

Alternatives and complementary repositories for arithmetic

• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆56Updated 10 months ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆47Updated 2 years ago
• chipsalliance / diplomacy
  ☆16Updated 4 months ago
• meton-robean / Vector_MulAdd_Accelerator
  vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
  ☆49Updated 4 years ago
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆48Updated 2 weeks ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 2 years ago
• sifive / block-inclusivecache-sifive
  ☆75Updated 2 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆49Updated 10 months ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆55Updated 2 weeks ago
• yaozhaosh / chisel-aes
  Chisel implementation of AES
  ☆23Updated 4 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆64Updated 4 months ago
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆60Updated 8 months ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆31Updated last year
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆26Updated 4 years ago
• chipsalliance / playground
  chipyard in mill :P
  ☆75Updated last year
• lingscale / cc01
  ☆31Updated last year
• rhit-neuro / deca
  ☆21Updated 4 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆28Updated 3 weeks ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆69Updated 4 years ago
• CherrySprings / CherrySprings
  ☆16Updated last year
• pulp-platform / fpu
  ☆37Updated 5 years ago
• samehattia / StateMover
  StateMover is a checkpoint-based debugging framework for FPGAs.
  ☆17Updated 2 years ago
• hushenwei2000 / rvv-atg
  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…
  ☆14Updated 7 months ago
• ljgibbslf / basic_cache_core
  ☆25Updated 4 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆64Updated 4 years ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆52Updated 4 years ago
• oscc-ip / sdram
  An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …
  ☆14Updated last month
• ucb-bar / chisel-gui
  A prototype GUI for chisel-development
  ☆52Updated 4 years ago
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆47Updated last year
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆35Updated 2 years ago