Alternatives and similar repositories for arithmetic:

Users that are interested in arithmetic are comparing it to the libraries listed below

• meton-robean / Vector_MulAdd_Accelerator
  vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
  ☆51Updated 4 years ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆18Updated last week
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 2 years ago
• OSCPU / chisel-playground
  ☆60Updated 3 weeks ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆59Updated 3 months ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆58Updated last year
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆50Updated 3 years ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆29Updated 3 months ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆54Updated last year
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated last year
• yaozhaosh / chisel-aes
  Chisel implementation of AES
  ☆23Updated 4 years ago
• hushenwei2000 / rvv-atg
  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…
  ☆14Updated 11 months ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆31Updated 2 years ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆37Updated 2 years ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆70Updated 5 years ago
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆26Updated 5 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆64Updated 7 months ago
• esa-tu-darmstadt / SCAIE-V
  An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:
  ☆14Updated last year
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆67Updated last year
• lizhirui / DreamCoreV2
  ☆21Updated last year
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆55Updated this week
• lingscale / cc01
  ☆31Updated this week
• chipsalliance / tilelink
  ☆27Updated 2 months ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆32Updated last year
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆16Updated last week
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆58Updated last year
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆52Updated 4 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆30Updated 4 months ago
• pku-liang / ksim
  ☆39Updated last month