RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor
☆20Jun 18, 2026Updated last month
Alternatives and similar repositories for vicuna2_core
Users that are interested in vicuna2_core are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆10Dec 15, 2023Updated 2 years ago
- matrix-coprocessor for RISC-V☆36Feb 27, 2026Updated 4 months ago
- 大三上做的本科毕设，包含BNN的替代梯度训练，verilog电路实现，完成180nm工艺流片。☆26Jun 30, 2025Updated last year
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆11Apr 13, 2026Updated 3 months ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆17Feb 29, 2024Updated 2 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- A Customized ASIC framework for Retro Stuff☆25Updated this week
- RISC-V Zve32x Vector Coprocessor☆221Jan 22, 2026Updated 5 months ago
- ☆15Jul 28, 2022Updated 3 years ago
- Template for project1 TPU☆23May 1, 2021Updated 5 years ago
- Scalable Interface for RISC-V ISA Extensions☆26Jun 9, 2026Updated last month
- Modified version of PULP Ara to support Vector Cryptography (Zvk) Instructions☆18Jan 21, 2026Updated 6 months ago
- Sail architecture definition language☆12Feb 1, 2025Updated last year
- RISC-V-5 stage pipelined in verilog☆10Jul 24, 2020Updated 5 years ago
- ☆19Dec 21, 2020Updated 5 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Extendable Translating Instruction Set Simulator☆43Jun 22, 2026Updated 3 weeks ago
- Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.☆23Updated this week
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 6 years ago
- Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022☆11Sep 21, 2022Updated 3 years ago
- Formal Verification of RISC V IM Processor☆11Mar 27, 2022Updated 4 years ago
- This repo includes XiangShan's function units☆32Updated this week
- vRTLmod modifies Verilator generated RTL simulation code for faul-injection purposes. It transforms source code with the help of LLVM/C…☆20Mar 28, 2026Updated 3 months ago
- 基于RISC_V32I指令集架构的五级流水CPU☆15Sep 30, 2019Updated 6 years ago
- RiVEC Bencmark Suite☆133Nov 27, 2024Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆18Apr 17, 2026Updated 3 months ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆21Updated this week
- This project contains a code generator that produces static C NN inference deployment code targeting tiny micro-controllers (TinyML) as r…☆30Sep 22, 2021Updated 4 years ago
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated last year
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 7 years ago
- 这是一个用chisel实现的FP8混合乘加单元☆18Jun 18, 2025Updated last year
- RISC-V Virtual Prototype☆49Oct 1, 2021Updated 4 years ago
- Chisel RISC-V Vector 1.0 Implementation☆153Jul 14, 2026Updated last week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆19Jan 13, 2026Updated 6 months ago
- Library of example SystemC/TLM peripherals for various SoCs based on the SCS library☆16Jun 29, 2026Updated 3 weeks ago
- xkDLA：XinKai Deep Learning Accelerator (RTL)☆44Jan 15, 2024Updated 2 years ago
- An open silicon CHERIoT Ibex microcontroller chip☆19May 23, 2025Updated last year
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆69Updated this week
- ☆14Feb 13, 2022Updated 4 years ago
- This is a brand new implement of GPGPU called Koala GPU which will be compatible with NV GPU micro architecture starting from fermi. It s…☆18May 31, 2026Updated last month