RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor
☆24Oct 23, 2026Updated last week
Alternatives and similar repositories for vicuna2_core
Users that are interested in vicuna2_core are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RISC-V Zve32x Vector Coprocessor☆224Jan 22, 2026Updated 9 months ago
- ☆10Dec 15, 2023Updated 2 years ago
- Seal5 - Semi-automated LLVM Support for RISC-V Extensions including Autovectorization☆25Updated this week
- An open-hardware co-design framework for deploying PyTorch models on RISC-V SoCs with custom ML accelerators, enabling rapid design spac…☆15Feb 12, 2025Updated last year
- Tensor computing core☆15Jul 8, 2026Updated 3 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆17Feb 29, 2024Updated 2 years ago
- matrix-coprocessor for RISC-V☆40Feb 27, 2026Updated 8 months ago
- Tool for the deployment and analysis of TinyML applications on TFLM and MicroTVM backends☆35Updated this week
- Topaz Computer☆15Jul 15, 2026Updated 3 months ago
- Scalable Interface for RISC-V ISA Extensions☆26Aug 13, 2026Updated 2 months ago
- Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.☆29Oct 23, 2026Updated last week
- 大三上做的本科毕设,包含BNN的替代梯度训练,verilog电路实现,完成180nm工艺流片。☆29Jun 30, 2025Updated last year
- muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.☆107Updated this week
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆11Apr 13, 2026Updated 6 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Tightly Coupled Bus, low complexity, high performance system bus.☆13Apr 16, 2026Updated 6 months ago
- Dual RISC-V DISC with integrated eFPGA☆18Oct 9, 2021Updated 5 years ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆264Oct 12, 2026Updated 2 weeks ago
- Example FPGA programs written using LegUp HLS☆11May 13, 2021Updated 5 years ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆140Updated this week
- npu☆13Sep 5, 2018Updated 8 years ago
- ☆13Jan 24, 2026Updated 9 months ago
- Template for project1 TPU☆23May 1, 2021Updated 5 years ago
- RTL and UVM test code of a Multi-NoC system☆12Dec 7, 2021Updated 4 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Modified version of PULP Ara to support Vector Cryptography (Zvk) Instructions☆16Jan 21, 2026Updated 9 months ago
- RISC-V-5 stage pipelined in verilog☆12Jul 24, 2020Updated 6 years ago
- ☆14Jun 9, 2026Updated 4 months ago
- RiVEC Bencmark Suite☆134Nov 27, 2024Updated last year
- A Customized ASIC framework for Retro Stuff☆37Updated this week
- RTL implementation of a performance/area optimized bfloat16 adder and multiplication.☆39Mar 28, 2026Updated 7 months ago
- Sail architecture definition language☆12Feb 1, 2025Updated last year
- The holy grail of preprocessor metaprogramming : (actually) turing complete macros☆10Mar 11, 2022Updated 4 years ago
- Xtext project to parse CoreDSL files☆24Jul 22, 2026Updated 3 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022☆11Sep 21, 2022Updated 4 years ago
- GEMM and GEMM-Ops accelerator for PULP systems☆126Oct 22, 2026Updated last week
- 基于RISC_V32I指令集架构的五级流水CPU☆15Sep 30, 2019Updated 7 years ago
- Tensor Compute Primitives: Mid-level Intermediate Representation for Machine Learning Programs☆14Jun 10, 2025Updated last year
- Nuclei AI Library Optimized For RISC-V Vector☆16Oct 15, 2025Updated last year
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 7 years ago
- ☆18Aug 17, 2026Updated 2 months ago