☆10Mar 4, 2025Updated last year
Alternatives and similar repositories for IC-Contest-Cell-Based
Users that are interested in IC-Contest-Cell-Based are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- IC-contest 2012~2024☆23Apr 30, 2024Updated 2 years ago
- ☆15May 30, 2021Updated 4 years ago
- ☆10Aug 30, 2024Updated last year
- Website for the OpenROAD tutorial held at the MICRO 2022 conference☆36Oct 6, 2022Updated 3 years ago
- 題目練習☆13Sep 29, 2022Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆35Jun 30, 2020Updated 5 years ago
- ☆14May 27, 2024Updated last year
- Integrated Circuit Design Contest (ICDC) - 大學院校積體電路設計競賽☆24Apr 20, 2022Updated 4 years ago
- NCTU 2021 Spring Integrated Circuit Design Laboratory☆203Apr 2, 2023Updated 3 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆76Jul 31, 2018Updated 7 years ago
- ☆33Jan 6, 2026Updated 3 months ago
- IC Contest☆47Mar 28, 2023Updated 3 years ago
- some interesting demos for starters☆96Dec 2, 2022Updated 3 years ago
- Student project for using audio on the DE2-115 FPGA development board.☆27Apr 28, 2018Updated 8 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- 楊家驤老師的"電腦輔助積體電路系統設計"作業(CVSD)☆43Oct 6, 2024Updated last year
- ☆26Sep 30, 2025Updated 7 months ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆140Jul 22, 2025Updated 9 months ago
- ☆125Jul 22, 2020Updated 5 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆148Mar 19, 2018Updated 8 years ago
- Generator of verilog description for FPGA MobileNet implementation☆185Jun 23, 2022Updated 3 years ago
- 💻 A 5-stage pipeline MIPS CPU implementation in Verilog.☆34Jul 5, 2020Updated 5 years ago
- ☆43Apr 6, 2023Updated 3 years ago
- Discussion Forum for High-Level Synthesis (HLS) Courses in Taiwan.☆57Sep 5, 2023Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆190Apr 10, 2023Updated 3 years ago
- ☆64Jul 2, 2025Updated 9 months ago
- ☆65Dec 3, 2021Updated 4 years ago
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆213Aug 23, 2023Updated 2 years ago
- 交通大學iclab 2023 fall☆46Oct 18, 2024Updated last year
- ☆106Nov 30, 2023Updated 2 years ago
- A Pytorch implementation of MoveNet from Google. Include training code and pre-trained model.☆415Jan 21, 2025Updated last year
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆617Apr 24, 2026Updated last week
- 使用Verilog实现的CNN模块,可以方便的在FPGA项目中使用☆591Jun 18, 2018Updated 7 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆208Jun 25, 2020Updated 5 years ago
- Research and Materials on Hardware implementation of Transformer Model☆306Feb 28, 2025Updated last year
- An open-source static random access memory (SRAM) compiler.☆1,048Apr 17, 2026Updated 2 weeks ago
- Tile based architecture designed for computing efficiency, scalability and generality☆289Mar 30, 2026Updated last month
- [ICML'21 Oral] I-BERT: Integer-only BERT Quantization☆268Jan 29, 2023Updated 3 years ago
- A PyTorch implementation of MobileNet V2 architecture and pretrained model.☆1,407Oct 20, 2019Updated 6 years ago
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆450Dec 2, 2019Updated 6 years ago