Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.
☆21Feb 28, 2021Updated 5 years ago
Alternatives and similar repositories for CNN-Accelerator
Users that are interested in CNN-Accelerator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Apr 10, 2020Updated 6 years ago
- Energy-Efficient Inference Accelerator for Memory-Augmented Neural Networks on an FPGA (DATE-19)☆15Jan 29, 2021Updated 5 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals,this SoC run a CNN. The…☆14Mar 30, 2023Updated 3 years ago
- IEEE Executive project for the year 2021-2022☆11Nov 22, 2022Updated 3 years ago
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- CNN-Accelerator based on FPGA developed by verilog HDL.☆11Jan 27, 2022Updated 4 years ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆167Dec 13, 2020Updated 5 years ago
- Hardware Acceleration of Banded Smith-Waterman Algorithm on an FPGA using Systolic array based architecture.☆12Nov 26, 2022Updated 3 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆18Jan 30, 2023Updated 3 years ago
- 🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*☆22May 27, 2024Updated 2 years ago
- ☆128Jul 22, 2020Updated 6 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆190Jun 20, 2024Updated 2 years ago
- ☆12Mar 9, 2018Updated 8 years ago
- VHDL implementation of carrier phase recovery (CPR) techniques for coherent optical systems☆16Dec 6, 2020Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- A CNN-based hardware digit/image recognition module designed on PyTorch and then implemented with Verilog on FPGA☆22Oct 17, 2022Updated 3 years ago
- Convolution Neural Network of vgg19 model in verilog☆50Jan 4, 2018Updated 8 years ago
- Verilog library for implementing neural networks.☆27Aug 19, 2014Updated 11 years ago
- Scripts, classes and functions related to Optical Wireless Communication☆15May 18, 2020Updated 6 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆17Jul 7, 2018Updated 8 years ago
- Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Syno…☆14Jun 9, 2021Updated 5 years ago
- CNN on Artix-7 FPGA to perform pattern detection from a pool of objects☆12Sep 12, 2018Updated 7 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆25Jul 6, 2018Updated 8 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Example of a full DC synthesis script for a simple design☆14Feb 25, 2019Updated 7 years ago
- An automated HDC platform☆11Mar 16, 2026Updated 4 months ago
- ☆18Jul 20, 2019Updated 7 years ago
- 在FPGA上部署深度学习项目☆25Mar 18, 2021Updated 5 years ago
- 一些小的工程记录☆25Feb 2, 2020Updated 6 years ago
- 使用Verilog实现的CNN模块,可以方便的在FPGA项目中使用☆590Jun 18, 2018Updated 8 years ago
- This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2☆17Jan 27, 2018Updated 8 years ago
- Maximum likelihood sequence estimation (MLSE) using the Viterbi algorithm☆17Feb 5, 2021Updated 5 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆29May 20, 2019Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆16Sep 28, 2017Updated 8 years ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆15Jul 14, 2019Updated 7 years ago
- Polarization Demultiplexing for Optical Communication Systems☆16Apr 20, 2023Updated 3 years ago
- A pipelined brainfuck softcore in Verilog☆20Aug 5, 2014Updated 11 years ago
- a hardware task scheduler design☆10Sep 14, 2022Updated 3 years ago
- TCL, verilog and shell scripts used while learning Cadence genus, innovus and tempus tools.☆17Oct 24, 2021Updated 4 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆64Jul 31, 2024Updated last year