Alternatives and similar repositories for Bitlet-PE

Users that are interested in Bitlet-PE are comparing it to the libraries listed below

• CASR-HKU / AGNA-FCCM2023
  ☆12Updated last year
• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆16Updated last year
• fffasttime / AnyPackingNet
  ☆26Updated last month
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆43Updated 2 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆77Updated 3 years ago
• CASR-HKU / DPACS
  ☆18Updated 2 years ago
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆20Updated 2 years ago
• KULeuven-MICAS / zigzag-llm
  Model LLM inference on single-core dataflow accelerators
  ☆10Updated 2 months ago
• pku-liang / Sanger
  A co-design architecture on sparse attention
  ☆52Updated 3 years ago
• jha-lab / acceltran
  [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers
  ☆41Updated last year
• sjtu-zhao-lab / SALO
  An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences
  ☆26Updated last year
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆51Updated last month
• SFU-HiAccel / HiSpMV
  [FPGA 2024]FPGA Accelerator for Imbalanced SpMV using HLS
  ☆12Updated 3 months ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆51Updated 2 weeks ago
• arc-research-lab / SSR
  SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)
  ☆31Updated this week
• abdelfattah-lab / BitMoD-HPCA-25
  ☆33Updated 4 months ago
• gem5-X / TiC-SAT
  ☆15Updated 10 months ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆38Updated 2 years ago
• OswaldHe / LevelST
  [FPGA 2024] Source code and bitstream for LevelST: Stream-based Accelerator for Sparse Triangular Solver
  ☆11Updated last year
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆51Updated last month
• maestro-project / gamma
  ☆40Updated 10 months ago
• mustard-seed / SparseDNNAccelerator
  Sparse CNN Accelerator targeting Intel FPGA
  ☆11Updated 3 years ago
• KyleParkJong / Network-on-Chip-Simulator
  Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
  ☆27Updated last year
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• ebby-s / MX-for-FPGA
  Implementation of Microscaling data formats in SystemVerilog.
  ☆18Updated 8 months ago
• KULeuven-MICAS / zigzag-imc
  HW accelerator mapping optimization framework for in-memory computing
  ☆22Updated 3 months ago
• lsq314 / SpMM_TCAD
  ☆16Updated 7 months ago
• horizon-research / systolic-array-dataflow-optimizer
  A general framework for optimizing DNN dataflow on systolic array
  ☆35Updated 4 years ago
• isakedo / DNNsim
  ☆34Updated 4 years ago
• gicLAB / SECDA
  ☆22Updated 2 years ago