Zhu-Zixuan / Bitlet-PELinks
A bit-level sparsity-awared multiply-accumulate process element.
☆18Updated last year
Alternatives and similar repositories for Bitlet-PE
Users that are interested in Bitlet-PE are comparing it to the libraries listed below
Sorting:
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆71Updated last month
- Open-source of MSD framework☆16Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆83Updated 4 years ago
- ☆18Updated 2 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 5 months ago
- Model LLM inference on single-core dataflow accelerators☆16Updated this week
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆54Updated 2 years ago
- ☆19Updated 6 months ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- ☆20Updated last year
- A co-design architecture on sparse attention☆54Updated 4 years ago
- ☆31Updated 8 months ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆42Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆91Updated last year
- ☆35Updated 5 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆69Updated 2 months ago
- ☆47Updated 4 years ago
- ☆50Updated last week
- bitfusion verilog implementation☆12Updated 3 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Updated 2 years ago
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆77Updated 7 months ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆35Updated last week
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆45Updated last year
- An FPGA Accelerator for Transformer Inference☆92Updated 3 years ago
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆21Updated 8 months ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆30Updated last year
- [FPGA 2024] Source code and bitstream for LevelST: Stream-based Accelerator for Sparse Triangular Solver☆14Updated 6 months ago
- ☆12Updated 2 years ago
- Implementation of Microscaling data formats in SystemVerilog.☆28Updated 5 months ago