Zhu-Zixuan / Bitlet-PE
A bit-level sparsity-awared multiply-accumulate process element.
☆14Updated 9 months ago
Alternatives and similar repositories for Bitlet-PE:
Users that are interested in Bitlet-PE are comparing it to the libraries listed below
- ☆15Updated 10 months ago
- Open-source of MSD framework☆16Updated last year
- ☆26Updated 3 weeks ago
- ☆18Updated 2 years ago
- Model LLM inference on single-core dataflow accelerators☆10Updated 2 months ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- ☆12Updated last year
- MICRO22 artifact evaluation for Sparseloop☆43Updated 2 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆51Updated 2 months ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆26Updated last year
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆40Updated last year
- A co-design architecture on sparse attention☆51Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆74Updated 3 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆48Updated 3 weeks ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆31Updated this week
- [FPGA 2024]FPGA Accelerator for Imbalanced SpMV using HLS☆12Updated 2 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆50Updated last month
- ☆28Updated 4 months ago
- ☆24Updated 8 months ago
- Sparse CNN Accelerator targeting Intel FPGA☆11Updated 3 years ago
- ☆16Updated 7 months ago
- Accelerate multihead attention transformer model using HLS for FPGA☆11Updated last year
- ☆16Updated 2 years ago
- [FPGA 2024] Source code and bitstream for LevelST: Stream-based Accelerator for Sparse Triangular Solver☆11Updated last year
- eyeriss-chisel3☆40Updated 2 years ago
- HW accelerator mapping optimization framework for in-memory computing☆22Updated 3 months ago
- Implementation of Microscaling data formats in SystemVerilog.☆17Updated 7 months ago
- A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.☆21Updated 9 months ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆38Updated 2 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 4 years ago