Alternatives and similar repositories for Bitlet-PE

Users that are interested in Bitlet-PE are comparing it to the libraries listed below

• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆80Updated 3 years ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆63Updated 3 weeks ago
• jha-lab / acceltran
  [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers
  ☆51Updated last year
• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆16Updated 2 years ago
• CASR-HKU / DPACS
  ☆18Updated 2 years ago
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆44Updated 3 years ago
• fffasttime / AnyPackingNet
  ☆28Updated 5 months ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆58Updated 2 months ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆84Updated last year
• KULeuven-MICAS / zigzag-llm
  Model LLM inference on single-core dataflow accelerators
  ☆14Updated last month
• pku-liang / Sanger
  A co-design architecture on sparse attention
  ☆51Updated 4 years ago
• lsq314 / SpMM_TCAD
  ☆17Updated last year
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆110Updated 5 years ago
• gem5-X / TiC-SAT
  ☆17Updated 4 months ago
• isakedo / DNNsim
  ☆35Updated 5 years ago
• arc-research-lab / SSR
  SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)
  ☆33Updated this week
• CASR-HKU / AGNA-FCCM2023
  ☆12Updated last year
• sjtu-zhao-lab / SALO
  An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences
  ☆29Updated last year
• ECASLab / hls-fpga-accelerators
  Collection of kernel accelerators optimised for LLM execution
  ☆21Updated 5 months ago
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆63Updated 6 months ago
• SFU-HiAccel / HiSpMV
  [TRETS 2025][FPGA 2024] FPGA Accelerator for Imbalanced SpMV using HLS
  ☆14Updated 3 weeks ago
• hatsu3 / Sanger
  ☆48Updated 4 years ago
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆20Updated 2 years ago
• mean9park / BitFusion-verilog
  bitfusion verilog implementation
  ☆12Updated 3 years ago
• abdelfattah-lab / BitMoD-HPCA-25
  ☆52Updated last month
• booniebears / CoMN
  ☆18Updated last year
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated 11 months ago
• cjg91 / trans-fat
  An FPGA Accelerator for Transformer Inference
  ☆88Updated 3 years ago
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• cornell-zhang / FracBNN
  FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
  ☆94Updated 3 years ago