Alternatives and similar repositories for lenet5-verilog

Users that are interested in lenet5-verilog are comparing it to the libraries listed below

• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆227Updated 2 years ago
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆163Updated last year
• boaaaang / CNN-Implementation-in-Verilog
  Convolutional Neural Network RTL-level Design
  ☆70Updated 3 years ago
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆35Updated 3 years ago
• Mattjesc / Efficient-FPGA-CNN-Accelerator
  Efficient FPGA-Based Accelerator for Convolutional Neural Networks
  ☆27Updated last year
• louislxw / pe_array
  A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…
  ☆12Updated last year
• yztong / LeNet_RTL
  An LeNet RTL implement onto FPGA
  ☆49Updated 7 years ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆17Updated 4 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆172Updated 5 years ago
• eda-lab / CNNAF-CNN-Accelerator_init
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆48Updated 5 years ago
• dldldlfma / super_small_toy_tpu
  ☆42Updated 4 years ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆118Updated 5 years ago
• sumanth-kalluri / cnn_hardware_acclerator_for_fpga
  This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…
  ☆187Updated last year
• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆27Updated 6 years ago
• amiq-consulting / CNN-using-HLS
  Convolutional Neural Network Using High Level Synthesis
  ☆88Updated 5 years ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆132Updated 4 months ago
• suchuankai / CNN-hw-accelerator
  CNN hardware accelerator to accelerate quantized LeNet-5 model
  ☆41Updated 2 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆109Updated 2 months ago
• padhi499 / Image-Classification-using-CNN-on-FPGA
  Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.
  ☆157Updated 4 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆104Updated 5 years ago
• zhan6841 / FPGA-Accelerator-for-AES-LeNet-VGG16
  FPGA/AES/LeNet/VGG16
  ☆108Updated 7 years ago
• kerryliukk / NTHU-ICLAB
  清華大學 | 積體電路設計實驗 (IC LAB) | 110上
  ☆45Updated 2 years ago
• abdelazeem201 / ASIC-implementation-of-AES
  Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…
  ☆22Updated 4 years ago
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆280Updated 11 months ago
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆46Updated 6 years ago
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆129Updated 7 years ago
• huangxc6 / E203_CNN_Genesys2
  Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.
  ☆21Updated last year
• chengquan / IC_FLOW
  ☆17Updated last year
• AniketBadhan / Convolutional-Neural-Network
  Implementation of CNN using Verilog
  ☆223Updated 7 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆77Updated 7 years ago