djtfoo / lenet5-verilog
A Verilog design of LeNet-5, a Convolutional Neural Network architecture
☆30Updated 4 years ago
Alternatives and similar repositories for lenet5-verilog:
Users that are interested in lenet5-verilog are comparing it to the libraries listed below
- An LeNet RTL implement onto FPGA☆45Updated 6 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 5 years ago
- ☆107Updated 4 years ago
- 使用FPGA实现CNN模型☆14Updated 5 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆65Updated 2 months ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆32Updated last year
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆11Updated 8 months ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆30Updated 2 years ago
- Convolutional Neural Network RTL-level Design☆51Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆155Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- 3×3脉动阵列乘法器☆44Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆98Updated 3 years ago
- Using verilog to implement MAC (Multiply Accumulate) . Verifying it by testbench .☆12Updated 6 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆98Updated 4 years ago
- Convolutional Neural Network Using High Level Synthesis☆86Updated 4 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆22Updated 4 years ago
- tpu-systolic-array-weight-stationary☆24Updated 3 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆149Updated 10 months ago
- ☆21Updated last year
- ☆63Updated 6 years ago
- Hardware accelerator for convolutional neural networks☆43Updated 2 years ago
- ☆38Updated 4 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- 3 layern artificial ANN to recognize handwritten digits and implement in FPGA☆8Updated 4 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 4 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Updated 7 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆71Updated last year