djtfoo / lenet5-verilogLinks
A Verilog design of LeNet-5, a Convolutional Neural Network architecture
☆34Updated 5 years ago
Alternatives and similar repositories for lenet5-verilog
Users that are interested in lenet5-verilog are comparing it to the libraries listed below
Sorting:
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- Convolutional Neural Network RTL-level Design☆68Updated 3 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆160Updated last year
- An LeNet RTL implement onto FPGA☆49Updated 7 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆222Updated 2 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆24Updated last year
- Systolic array based simple TPU for CNN on PYNQ-Z2☆35Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆166Updated 5 years ago
- Convolutional Neural Network Using High Level Synthesis☆88Updated 4 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆186Updated last year
- FPGA/AES/LeNet/VGG16☆108Updated 7 years ago
- ☆42Updated 4 years ago
- ☆115Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆40Updated last year
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆44Updated 2 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆12Updated last year
- ☆17Updated last year
- 3×3脉动阵列乘法器☆47Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆132Updated 4 months ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆155Updated 4 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆104Updated 4 years ago
- Implementation of CNN using Verilog☆224Updated 7 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆100Updated last month
- 使用FPGA实现CNN模型☆15Updated 6 years ago
- Using verilog to implement MAC (Multiply Accumulate) . Verifying it by testbench .☆12Updated 6 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆20Updated 4 years ago