ac-optimus / Convolution-using-systolic-arraysLinks
☆71Updated 6 years ago
Alternatives and similar repositories for Convolution-using-systolic-arrays
Users that are interested in Convolution-using-systolic-arrays are comparing it to the libraries listed below
Sorting:
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆82Updated 2 years ago
- A systolic array matrix multiplier☆29Updated 6 years ago
- IC implementation of TPU☆138Updated 5 years ago
- Hardware accelerator for convolutional neural networks☆60Updated 3 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆32Updated 4 years ago
- Verilog implementation of Softmax function☆77Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆177Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆108Updated 5 years ago
- ☆121Updated 5 years ago
- ☆38Updated 6 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆68Updated last week
- Systolic array based simple TPU for CNN on PYNQ-Z2☆39Updated 3 years ago
- ☆66Updated 3 years ago
- HLS implemented systolic array structure☆41Updated 8 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆204Updated 5 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- Systolic-array based Deep Learning Accelerator generator☆27Updated 4 years ago
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆142Updated 6 months ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Updated 4 years ago
- ☆44Updated 4 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆97Updated last week
- Convolutional accelerator kernel, target ASIC & FPGA☆235Updated 2 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆157Updated 8 months ago
- 3×3脉动阵列乘法器☆48Updated 6 years ago