An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017
☆28May 20, 2019Updated 7 years ago
Alternatives and similar repositories for LeNet-CNN-Accelerator-Hardware-for-FPGA
Users that are interested in LeNet-CNN-Accelerator-Hardware-for-FPGA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- FPGA Innovation Design Competition：RISC-V Processor-based Hardware and Software Design in PGL22G☆12Sep 1, 2023Updated 2 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆242Oct 16, 2025Updated 7 months ago
- ☆14Aug 23, 2023Updated 2 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆14Aug 26, 2021Updated 4 years ago
- Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…☆16Apr 12, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Verilog Sigmoid and Tanh functions which can be configured and added to your neural network project☆17Mar 9, 2020Updated 6 years ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 9 years ago
- ☆19Dec 19, 2018Updated 7 years ago
- bitfusion verilog implementation☆13Feb 21, 2022Updated 4 years ago
- (Verilog) A simple convolution layer implementation with systolic array structure☆13May 9, 2022Updated 4 years ago
- 使用FPGA实现CNN模型☆15Jun 21, 2019Updated 6 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆31Nov 5, 2021Updated 4 years ago
- The code of SpikingSSMs: Learning Long Sequences with Sparse and Parallel Spiking State Space Models☆23Mar 25, 2026Updated 2 months ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- ☆16Apr 24, 2023Updated 3 years ago
- Tensor Processing Unit implementation in Verilog☆14Mar 18, 2025Updated last year
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆37Dec 22, 2023Updated 2 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆46Jun 24, 2022Updated 3 years ago
- ☆33Nov 7, 2024Updated last year
- ☆33Aug 23, 2023Updated 2 years ago
- Dual-tree complex wavelet combined with non-local means ASL fMRI denoising is a software toolbox that can denoise MR images, especially A…☆11Dec 14, 2017Updated 8 years ago
- super-resolution; post-training quantization; model compression☆14Nov 10, 2023Updated 2 years ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆165Dec 13, 2020Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- In this project, Image Denoising is considered for two cases. The first one is additive Gaussian noise while the second one is speckle no…☆12Nov 28, 2018Updated 7 years ago
- Router 1 x 3 verilog implementation☆15Sep 5, 2021Updated 4 years ago
- Deep learning accelerator for convolutional layer (convolution operation) and fully-connected layer(matrix-multiplication).☆20Nov 18, 2018Updated 7 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Aug 26, 2023Updated 2 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Feb 28, 2021Updated 5 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆23Aug 10, 2018Updated 7 years ago
- ☆68Apr 30, 2025Updated last year
- Hardware and software implementation of Sparsely-active SNNs☆22Mar 6, 2026Updated 2 months ago
- verilog实现systolic array及配套IO☆13Dec 2, 2024Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A 2D mesh Network on Chip with 5-stage pipelined router, all implemented in Verilog and run on Artix-7 FPGA.☆20May 30, 2023Updated 2 years ago
- ☆16Mar 18, 2025Updated last year
- Training Quantized Neural Networks with a Full-precision Auxiliary Module☆13Jun 19, 2020Updated 5 years ago
- Fast Relaxed Vector Fitting Implementation in C++☆15Apr 17, 2023Updated 3 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆13May 14, 2019Updated 7 years ago
- ☆73Dec 12, 2018Updated 7 years ago
- A project I made to practice my newfound Neural Network knowledge - I used Python and Numpy to train a network to recognize MNIST images.…☆11Mar 12, 2022Updated 4 years ago