An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017
☆23May 20, 2019Updated 6 years ago
Alternatives and similar repositories for LeNet-CNN-Accelerator-Hardware-for-FPGA
Users that are interested in LeNet-CNN-Accelerator-Hardware-for-FPGA are comparing it to the libraries listed below
Sorting:
- FPGA Innovation Design Competition：RISC-V Processor-based Hardware and Software Design in PGL22G☆12Sep 1, 2023Updated 2 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆224Oct 16, 2025Updated 4 months ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- Tensor Processing Unit implementation in Verilog☆13Mar 18, 2025Updated 11 months ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- ☆13Aug 23, 2023Updated 2 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆37Dec 22, 2023Updated 2 years ago
- Hardware accelerator for convolutional neural networks☆66Aug 9, 2022Updated 3 years ago
- Router 1 x 3 verilog implementation☆15Sep 5, 2021Updated 4 years ago
- bitfusion verilog implementation☆12Feb 21, 2022Updated 4 years ago
- (Verilog) A simple convolution layer implementation with systolic array structure☆13May 9, 2022Updated 3 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆12Aug 26, 2021Updated 4 years ago
- Verilog Sigmoid and Tanh functions which can be configured and added to your neural network project☆16Mar 9, 2020Updated 5 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Aug 26, 2023Updated 2 years ago
- A 2D mesh Network on Chip with 5-stage pipelined router, all implemented in Verilog and run on Artix-7 FPGA.☆17May 30, 2023Updated 2 years ago
- Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…☆16Apr 12, 2020Updated 5 years ago
- The code of SpikingSSMs: Learning Long Sequences with Sparse and Parallel Spiking State Space Models☆22Apr 16, 2025Updated 10 months ago
- ☆14Apr 24, 2023Updated 2 years ago
- Hardware and software implementation of Sparsely-active SNNs☆22Feb 25, 2026Updated last week
- 使用FPGA实现CNN模型☆15Jun 21, 2019Updated 6 years ago
- ☆19Dec 19, 2018Updated 7 years ago
- ☆15Mar 18, 2025Updated 11 months ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆45Jun 24, 2022Updated 3 years ago
- Deep learning accelerator for convolutional layer (convolution operation) and fully-connected layer(matrix-multiplication).☆20Nov 18, 2018Updated 7 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆23Aug 10, 2018Updated 7 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆33Aug 13, 2024Updated last year
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆25Nov 2, 2015Updated 10 years ago
- An automated HDC platform☆11Updated this week
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆85Nov 26, 2025Updated 3 months ago
- This repository contains full code of Softmax Layer in Verilog☆21Jul 29, 2020Updated 5 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Feb 28, 2021Updated 5 years ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆164Dec 13, 2020Updated 5 years ago
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 6 years ago
- This project is to design yolo AI accelerator in verilog HDL.☆34Oct 8, 2024Updated last year
- ☆33Aug 23, 2023Updated 2 years ago
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…☆22Nov 27, 2025Updated 3 months ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆28Nov 5, 2021Updated 4 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆29Feb 6, 2023Updated 3 years ago
- ☆32Jan 23, 2021Updated 5 years ago