jasonlin316 / Systolic-Array-for-Smith-WatermanView external linksLinks
This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times faster than a software running the same algorithm.
☆27Jul 4, 2019Updated 6 years ago
Alternatives and similar repositories for Systolic-Array-for-Smith-Waterman
Users that are interested in Systolic-Array-for-Smith-Waterman are comparing it to the libraries listed below
Sorting:
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13May 26, 2016Updated 9 years ago
- A general framework for optimizing DNN dataflow on systolic array☆38Jan 2, 2021Updated 5 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆23Jul 29, 2022Updated 3 years ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 4 years ago
- ☆73Dec 12, 2018Updated 7 years ago
- (Verilog) A simple convolution layer implementation with systolic array structure☆13May 9, 2022Updated 3 years ago
- Systolic-array based Deep Learning Accelerator generator☆28Dec 11, 2020Updated 5 years ago
- Verilog Sigmoid and Tanh functions which can be configured and added to your neural network project☆16Mar 9, 2020Updated 5 years ago
- ☆14Apr 8, 2025Updated 10 months ago
- Chisel3 implementation of IEEE-754 compliant floating point data type (logic & representation)☆11Dec 16, 2019Updated 6 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆17Feb 27, 2021Updated 4 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆15Nov 9, 2014Updated 11 years ago
- ES-203 Computer Organization & Architecture CNN on FPGA board☆17Feb 23, 2022Updated 3 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆17Jan 30, 2023Updated 3 years ago
- Falcon Accelerated Genomics Pipelines☆15Oct 1, 2019Updated 6 years ago
- This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2☆17Jan 27, 2018Updated 8 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Mar 5, 2018Updated 7 years ago
- Fast Floating Point Operators for High Level Synthesis☆23Feb 23, 2023Updated 2 years ago
- HLS implemented systolic array structure☆41Nov 13, 2017Updated 8 years ago
- course design☆23Feb 28, 2018Updated 7 years ago
- An automated HDC platform☆11Updated this week
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆82Nov 26, 2025Updated 2 months ago
- Template for project1 TPU☆23May 1, 2021Updated 4 years ago
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…☆22Nov 27, 2025Updated 2 months ago
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 6 years ago
- IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures☆29Jul 7, 2019Updated 6 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆36Dec 22, 2023Updated 2 years ago
- ☆71Mar 22, 2020Updated 5 years ago
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆32Nov 7, 2024Updated last year
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆36Sep 25, 2019Updated 6 years ago
- Implementing Different Adder Structures in Verilog☆74Sep 3, 2019Updated 6 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆32Sep 22, 2018Updated 7 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆159May 10, 2025Updated 9 months ago
- EE 272B - VLSI Design Project☆15Jun 24, 2021Updated 4 years ago
- ☆13Jan 8, 2020Updated 6 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆40May 17, 2022Updated 3 years ago
- ☆11Mar 14, 2023Updated 2 years ago
- Accelerator for Hyperdimensional Computing (HDC)☆35May 5, 2024Updated last year