jasonlin316 / Systolic-Array-for-Smith-Waterman
This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times faster than a software running the same algorithm.
☆22Updated 5 years ago
Alternatives and similar repositories for Systolic-Array-for-Smith-Waterman:
Users that are interested in Systolic-Array-for-Smith-Waterman are comparing it to the libraries listed below
- cycle accurate Network-on-Chip Simulator☆26Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆68Updated 3 years ago
- Ratatoskr NoC Simulator☆24Updated 3 years ago
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆12Updated 4 years ago
- CNN accelerator☆27Updated 7 years ago
- HLS for Networks-on-Chip☆33Updated 4 years ago
- ☆71Updated 2 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆48Updated 7 years ago
- ☆24Updated 5 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 4 years ago
- ☆62Updated 6 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆22Updated 2 years ago
- The Verilog source code for DRUM approximate multiplier.☆29Updated last year
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆22Updated 3 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆22Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆50Updated 2 weeks ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆32Updated 5 months ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆30Updated this week
- course design☆22Updated 7 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆24Updated 2 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- ☆34Updated 3 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆12Updated 4 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆12Updated 8 years ago