MT29F128G based NAND flash controller
☆10Jun 17, 2021Updated 4 years ago
Alternatives and similar repositories for NAND-Flash-controller
Users that are interested in NAND-Flash-controller are comparing it to the libraries listed below
Sorting:
- ☆18Jun 3, 2019Updated 6 years ago
- AXI Interface Nand Flash Controller (Sync mode)☆103Aug 9, 2024Updated last year
- AXI-4 RAM Tester Component☆21Aug 5, 2020Updated 5 years ago
- AXI4 BFM in Verilog☆36Dec 13, 2016Updated 9 years ago
- Pipeline CPU of MIPS architecture with L1 Data Cache by Verilog☆20Mar 11, 2021Updated 5 years ago
- Open-Channel Open-Way Flash Controller☆22Sep 10, 2021Updated 4 years ago
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- Implements a simple UVM based testbench for a simple memory DUT.☆13Oct 26, 2019Updated 6 years ago
- Simple test of ARM NEON code. Performs a blit to the framebuffer.☆15Jul 23, 2013Updated 12 years ago
- ☆31Aug 8, 2020Updated 5 years ago
- This repository contains verilog files to implement Reed Solomon encoding and decoding on FPGA. Each symbol is of 8 bits. Message length …☆23Dec 17, 2019Updated 6 years ago
- ☆31Apr 1, 2017Updated 8 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Oct 7, 2020Updated 5 years ago
- A convolution based 3x3 GaussianBlur implementation using ARM NEON assembly engine☆10Jan 20, 2019Updated 7 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Aug 28, 2016Updated 9 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Aug 28, 2023Updated 2 years ago
- Pipelined MIPS architecture created in Verilog. Includes data forwarding and hazard detection.☆16Apr 1, 2018Updated 7 years ago
- RTL for mipi serialize and deserialize☆11Oct 16, 2017Updated 8 years ago
- The Subutai™ Router open hardware project sources.☆15Oct 2, 2017Updated 8 years ago
- Gaussian noise generator Verilog IP core☆33May 22, 2023Updated 2 years ago
- Tensor Processing Unit implementation in Verilog☆13Mar 18, 2025Updated last year
- ☆45Apr 11, 2017Updated 8 years ago
- A Verilog implementation of a processor cache.☆37Dec 29, 2017Updated 8 years ago
- Verilog CAN controller that is compatible to the SJA 1000.☆16Apr 17, 2021Updated 4 years ago
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago
- 简单易用的微信小程序倒计时库☆15May 15, 2018Updated 7 years ago
- USB2.0 Device Controller IP Core☆15Aug 18, 2023Updated 2 years ago
- YoudaoNote to WizNote，有道云笔记数据迁移为知笔记☆12Dec 4, 2018Updated 7 years ago
- ☆11Jun 28, 2020Updated 5 years ago
- MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement☆13Nov 4, 2022Updated 3 years ago
- Mirror of NeTV FPGA Verilog Code☆15Jan 21, 2012Updated 14 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆35May 12, 2020Updated 5 years ago
- Hex Calculator for Windows☆13Dec 2, 2016Updated 9 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The…☆13Mar 30, 2023Updated 2 years ago
- HDL and C source for WAVE Zynq Ultrascale+ SoC☆19Nov 16, 2021Updated 4 years ago
- AXI4-Stream FIR filter IP☆19Nov 4, 2022Updated 3 years ago
- Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-…☆30Dec 14, 2020Updated 5 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆12Jul 28, 2021Updated 4 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆17Feb 27, 2021Updated 5 years ago