debtanu09 / systolic_array_matrix_multiplierLinks
This is a verilog implementation of 4x4 systolic array multiplier
☆71Updated 5 years ago
Alternatives and similar repositories for systolic_array_matrix_multiplier
Users that are interested in systolic_array_matrix_multiplier are comparing it to the libraries listed below
Sorting:
- IC implementation of TPU☆143Updated 6 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆109Updated 5 years ago
- ☆39Updated 6 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆100Updated last week
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆75Updated last month
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆97Updated 6 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆33Updated 4 years ago
- Verilog implementation of Softmax function☆78Updated 3 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆140Updated 7 years ago
- ☆71Updated 7 years ago
- A verilog implementation for Network-on-Chip☆78Updated 7 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆40Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆177Updated 6 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago
- Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256☆27Updated last year
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆41Updated last year
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆158Updated 9 months ago
- AMD University Program HLS tutorial☆121Updated last year
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆55Updated last year
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆123Updated 5 months ago
- Verilog Implementation of 32-bit Floating Point Adder☆44Updated 5 years ago
- IC implementation of Systolic Array for TPU☆317Updated last year
- Hardware accelerator for convolutional neural networks☆60Updated 3 years ago
- An AXI4 crossbar implementation in SystemVerilog☆196Updated 3 months ago
- eyeriss-chisel3☆40Updated 3 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆236Updated 2 years ago
- ☆123Updated 5 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆73Updated 5 years ago