debtanu09 / systolic_array_matrix_multiplierLinks
This is a verilog implementation of 4x4 systolic array multiplier
☆57Updated 4 years ago
Alternatives and similar repositories for systolic_array_matrix_multiplier
Users that are interested in systolic_array_matrix_multiplier are comparing it to the libraries listed below
Sorting:
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆85Updated last month
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆76Updated last year
- Systolic array based simple TPU for CNN on PYNQ-Z2☆33Updated 3 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆87Updated 6 years ago
- A verilog implementation for Network-on-Chip☆74Updated 7 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- ☆34Updated 6 years ago
- IC implementation of TPU☆127Updated 5 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆126Updated 7 years ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆58Updated 11 months ago
- ☆65Updated 6 years ago
- Verilog implementation of Softmax function☆67Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆51Updated 9 months ago
- An AXI4 crossbar implementation in SystemVerilog☆161Updated 3 weeks ago
- IC implementation of Systolic Array for TPU☆257Updated 8 months ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆152Updated 2 years ago
- ☆47Updated 2 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆58Updated last week
- Vector processor for RISC-V vector ISA