debtanu09 / systolic_array_matrix_multiplier
This is a verilog implementation of 4x4 systolic array multiplier
☆38Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for systolic_array_matrix_multiplier
- IC implementation of TPU☆86Updated 4 years ago
- tpu-systolic-array-weight-stationary☆18Updated 3 years ago
- ☆26Updated 5 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆21Updated 2 years ago
- ☆60Updated 5 years ago
- Two Level Cache Controller implementation in Verilog HDL