hngenc / systolic-array
A DSL for Systolic Arrays
☆79Updated 6 years ago
Alternatives and similar repositories for systolic-array:
Users that are interested in systolic-array are comparing it to the libraries listed below
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆68Updated 5 years ago
- ☆71Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆77Updated 7 months ago
- ☆57Updated last year
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆55Updated 3 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆48Updated 3 weeks ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 weeks ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆86Updated 5 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆121Updated this week
- RTL implementation of Flex-DPE.☆98Updated 5 years ago
- ☆87Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆63Updated 3 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆119Updated 4 years ago
- ☆54Updated this week
- ☆84Updated 9 months ago
- ☆22Updated 4 months ago
- Tool for optimize CNN blocking☆93Updated 4 years ago
- ☆47Updated 3 weeks ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆48Updated this week
- An Open-Hardware CGRA for accelerated computation on the edge.☆20Updated 6 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆63Updated last week
- A hardware synthesis framework with multi-level paradigm☆38Updated 2 months ago
- ☆57Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆130Updated 2 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆58Updated 5 months ago
- Release of stream-specialization software/hardware stack.☆120Updated last year
- ☆34Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆69Updated 3 years ago