32 - bit floating point Multiplier Accumulator Unit (MAC)
☆34Jan 12, 2021Updated 5 years ago
Alternatives and similar repositories for Floating-point-MAC-verilog
Users that are interested in Floating-point-MAC-verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Jun 5, 2020Updated 5 years ago
- Systolic-array based Deep Learning Accelerator generator☆29Dec 11, 2020Updated 5 years ago
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 5 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Mar 5, 2018Updated 8 years ago
- ☆16Oct 20, 2025Updated 7 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- LSTM neural network (verilog)☆16Dec 5, 2018Updated 7 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆84Aug 3, 2023Updated 2 years ago
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆11Aug 15, 2020Updated 5 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆99Apr 30, 2019Updated 7 years ago
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 6 years ago
- Hardware Division Units☆10Jul 17, 2014Updated 11 years ago
- Verilog Implementation of 32-bit Floating Point Adder☆49May 4, 2020Updated 6 years ago
- （Not actively updating）Vision Transformer Accelerator implemented in Vivado HLS for Xilinx FPGAs.☆20Dec 29, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆73Dec 12, 2018Updated 7 years ago
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 3 years ago
- Template for project1 TPU☆23May 1, 2021Updated 5 years ago
- ☆30Dec 12, 2022Updated 3 years ago
- vector accelerating unit☆35Dec 1, 2020Updated 5 years ago
- IC implementation of Systolic Array for TPU☆357Oct 21, 2024Updated last year
- A CIC filter implemented in Verilog☆24Sep 7, 2015Updated 10 years ago
- SpinalHDL AdderNet MNIST☆11Feb 26, 2021Updated 5 years ago
- Python code to show how a systolic array works. Written for https://medium.com/@antonpaquin/whats-inside-a-tpu-c013eb51973e☆29Jun 8, 2018Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Jul 14, 2021Updated 4 years ago
- An UVM example of UART☆20Aug 31, 2020Updated 5 years ago
- ☆10Jan 3, 2022Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Apr 10, 2020Updated 6 years ago
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 6 years ago
- Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder☆122Jan 26, 2013Updated 13 years ago
- ☆13Apr 16, 2022Updated 4 years ago
- Convert single precision float to bfloat16 (Brain Floating Point) floating-point format☆14Oct 24, 2019Updated 6 years ago
- Modular Verilog PCIexpress Interface Components with complete MyHDL Testbench for FPGA deployment☆14Sep 17, 2019Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆25Jun 28, 2019Updated 6 years ago
- syn script for DC Compiler☆14May 15, 2022Updated 4 years ago
- Memory Compiler Tutorial☆14Aug 2, 2022Updated 3 years ago
- This is the final project for the BP NN FPGA implementation☆11Jan 14, 2017Updated 9 years ago
- ☆17Sep 16, 2022Updated 3 years ago
- A simple app written by Python3 for MMPI☆21Jul 1, 2020Updated 5 years ago
- An MIPS pipelined processor with hazard detection for the course VE370 (FA2020) at UMJI.☆11Dec 28, 2020Updated 5 years ago