Alternatives and similar repositories for Floating-point-MAC-verilog

Users that are interested in Floating-point-MAC-verilog are comparing it to the libraries listed below

• kuladeepsaireddy / OpenNoc
  ☆33Updated 6 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆24Updated 4 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆74Updated last year
• ac-optimus / Convolution-using-systolic-arrays
  ☆64Updated 6 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆100Updated 4 years ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆16Updated 3 years ago
• alireza-shirzad / Cordic_tanh
  Verilog and matlab implementation of tanh using Cordic algorithm
  ☆9Updated 4 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆73Updated 7 years ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆43Updated 2 years ago
• neasotho / SystolicArray_FPGA
  Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board
  ☆14Updated 4 years ago
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆31Updated 2 years ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆110Updated 4 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆159Updated 5 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆56Updated 2 months ago
• gju06051 / TPU_HW_Verilog
  ☆14Updated 2 years ago
• wzc810049078 / systolic-array-matrix-multiplier
  A systolic array matrix multiplier
  ☆24Updated 5 years ago
• hyoukjun / microswitch-noc
  ☆27Updated 5 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆49Updated last year
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆45Updated 5 years ago
• maomran / softmax
  Verilog implementation of Softmax function
  ☆65Updated 2 years ago
• ahirsharan / 32-Bit-Floating-Point-Adder
  Verilog Implementation of 32-bit Floating Point Adder
  ☆40Updated 5 years ago
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆30Updated 2 years ago
• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆27Updated 6 years ago
• canbozaci / Cache
  L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC
  ☆11Updated 2 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆37Updated 2 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆34Updated 4 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆40Updated 3 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆38Updated 2 years ago
• djtfoo / lenet5-verilog
  A Verilog design of LeNet-5, a Convolutional Neural Network architecture
  ☆31Updated 4 years ago