Template for project1 TPU
☆23May 1, 2021Updated 5 years ago
Alternatives and similar repositories for AIC2021_TPU_Template
Users that are interested in AIC2021_TPU_Template are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- AI Chip project☆34Jul 14, 2021Updated 4 years ago
- AIChip 2021 project, NCKU☆18May 6, 2021Updated 5 years ago
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 5 years ago
- Small-scale Tensor Processing Unit built on an FPGA☆227Aug 4, 2019Updated 6 years ago
- ☆53Jan 14, 2021Updated 5 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- IC implementation of TPU☆153Dec 18, 2019Updated 6 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆23Apr 25, 2025Updated last year
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆25May 19, 2026Updated last week
- ☆10Dec 15, 2023Updated 2 years ago
- RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor☆19Apr 8, 2026Updated last month
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- Tensor Processing Unit implementation in Verilog☆14Mar 18, 2025Updated last year
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆22Nov 9, 2025Updated 6 months ago
- RTL implementation of a ray-tracing GPU☆16Dec 18, 2012Updated 13 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- ☆12Jun 22, 2023Updated 2 years ago
- ☆35Apr 20, 2021Updated 5 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Jun 5, 2020Updated 5 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Jul 14, 2021Updated 4 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- ☆10Oct 8, 2021Updated 4 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13May 26, 2016Updated 10 years ago
- ☆16Apr 24, 2023Updated 3 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆12Nov 24, 2023Updated 2 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆30Mar 13, 2025Updated last year
- This repository contains the hardware implementation for Static BFP convolution on FPGA☆10Oct 15, 2019Updated 6 years ago
- AES☆15Oct 4, 2022Updated 3 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆18Feb 27, 2021Updated 5 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- 第四届全国大学生嵌入式比赛SoC☆12Apr 1, 2022Updated 4 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆19Jul 9, 2024Updated last year
- Verilog program☆16Jul 27, 2020Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 9 years ago
- Formal Verification of RISC V IM Processor☆11Mar 27, 2022Updated 4 years ago
- ☆15Mar 24, 2023Updated 3 years ago
- This is a simple Risc-v core for software simulation on FPGA.☆10Apr 9, 2022Updated 4 years ago
- Netrace: a network packet trace reader☆14Jun 16, 2014Updated 11 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆94Nov 26, 2025Updated 6 months ago
- verilog/FPGA hardware description for very simple GPU☆16Apr 9, 2019Updated 7 years ago