AIC2021 / AIC2021_TPU_TemplateLinks
Template for project1 TPU
☆19Updated 4 years ago
Alternatives and similar repositories for AIC2021_TPU_Template
Users that are interested in AIC2021_TPU_Template are comparing it to the libraries listed below
Sorting:
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆71Updated last week
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- ☆28Updated 6 years ago
- ☆36Updated last month
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆35Updated last year
- ☆38Updated 6 years ago
- Ratatoskr NoC Simulator☆28Updated 4 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- HLS for Networks-on-Chip☆37Updated 4 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Updated 2 years ago
- ☆19Updated 6 months ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Updated 2 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆28Updated 3 months ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆25Updated last year
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆21Updated 2 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆49Updated 9 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆83Updated 4 years ago
- A systolic array matrix multiplier☆29Updated 6 years ago
- A scalable Eyeriss model in SystemC.☆31Updated 2 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆71Updated 5 years ago
- ☆58Updated 7 months ago
- ☆31Updated 5 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago
- ☆15Updated 3 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆60Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- Hardware accelerator for convolutional neural networks☆60Updated 3 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆27Updated 6 years ago