Python code to show how a systolic array works. Written for https://medium.com/@antonpaquin/whats-inside-a-tpu-c013eb51973e
☆29Jun 8, 2018Updated 7 years ago
Alternatives and similar repositories for SystolicArrayDemo
Users that are interested in SystolicArrayDemo are comparing it to the libraries listed below
Sorting:
- This repository is an excuse to learn about Convolutional Neural Networks by implementing one in FPGA. The main goal is to learn, and to …☆12Jul 12, 2020Updated 5 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆22Jun 1, 2021Updated 4 years ago
- C++ SystemC Implementation of a Systolic Array☆15May 15, 2020Updated 5 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆17Feb 27, 2021Updated 5 years ago
- ☆73Dec 12, 2018Updated 7 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆23Jul 29, 2022Updated 3 years ago
- HLS implemented systolic array structure☆41Nov 13, 2017Updated 8 years ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆25Nov 2, 2015Updated 10 years ago
- An automated HDC platform☆11Updated this week
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 6 years ago
- Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256☆29Feb 21, 2024Updated 2 years ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆44Oct 31, 2025Updated 4 months ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆32Sep 22, 2018Updated 7 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆33Jan 12, 2021Updated 5 years ago
- EE 272B - VLSI Design Project☆15Jun 24, 2021Updated 4 years ago
- Reference workloads for modern deep learning methods.☆73Dec 14, 2022Updated 3 years ago
- A open source reimplementation of Google's Tensor Processing Unit (TPU).☆735Dec 6, 2017Updated 8 years ago
- pytorch fixed point training tool/framework☆34Oct 14, 2020Updated 5 years ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- ☆10Mar 18, 2020Updated 5 years ago
- Eyeriss chip simulator☆39Mar 6, 2020Updated 5 years ago
- Highly concurrent and fast content processing for Mighty Inference Server☆10Feb 6, 2023Updated 3 years ago
- ☆10Apr 21, 2025Updated 10 months ago
- (Original: code.google.com/p/pylinda) A Linda implementation in Python.☆12Jun 16, 2022Updated 3 years ago
- ☆11Nov 24, 2020Updated 5 years ago
- Neuromorphic ASIC with 96 neurons on Tiny Tapeout 7☆11May 25, 2024Updated last year
- Tools for computing quasinormal modes in Schwarzschild and Kerr spacetime☆12Sep 14, 2025Updated 5 months ago
- Code for the ISCAS23 paper "The Hardware Impact of Quantization and Pruning for Weights in Spiking Neural Networks"☆11Apr 20, 2023Updated 2 years ago
- Human activity recognition using hyperdimensional computing based on Kinect's skeleton data☆11Jun 5, 2017Updated 8 years ago
- Tensor Processing Unit implementation in Verilog☆13Mar 18, 2025Updated 11 months ago
- A library that you can use to build spiking neural network brains for your Arduino robots! Largely allows you to follow the paradigms of …☆10Nov 21, 2015Updated 10 years ago
- The VD100 development board is based on the Xilinx Versal AI Edge series chip xcve2302 and is designed with a core board and a bottom boa…☆18Jul 9, 2024Updated last year
- Integrating Event-based Dynamic Vision Sensors with Sparse Hyperdimensional Computing☆12Jul 9, 2020Updated 5 years ago
- TTK website☆11Jan 8, 2026Updated last month
- ☆10Jun 28, 2019Updated 6 years ago
- Multi-path UDP protocol - an example implementation☆10Jul 6, 2015Updated 10 years ago
- Cayley Dickson algebra implementation in python☆12Jan 3, 2019Updated 7 years ago
- This repository contains the models and training scripts used in the papers: "Quantizing Spiking Neural Networks with Integers" (ICONS 20…☆13Oct 20, 2020Updated 5 years ago
- A Verilog implementation of a hand-written digit recognition Neural Network☆10Nov 16, 2024Updated last year