hyupupup / conv_systolic_array
(Verilog) A simple convolution layer implementation with systolic array structure
☆12Updated 2 years ago
Alternatives and similar repositories for conv_systolic_array:
Users that are interested in conv_systolic_array are comparing it to the libraries listed below
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆14Updated 5 years ago
- Open-source of MSD framework☆16Updated last year
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 4 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆36Updated last month
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆83Updated 3 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆48Updated 3 weeks ago
- A collection of tutorials for the fpgaConvNet framework.☆40Updated 5 months ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆29Updated last year
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- C++ code for HLS FPGA implementation of transformer☆15Updated 6 months ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆48Updated 2 weeks ago
- ☆33Updated this week
- [TVLSI'23] This repository contains the source code for the paper "FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Net…☆16Updated 11 months ago
- ☆11Updated 10 months ago
- ☆103Updated 4 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆36Updated last year
- Hardware accelerator for convolutional neural networks☆36Updated 2 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆13Updated 8 months ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- ☆14Updated 5 months ago
- ☆25Updated 2 months ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆36Updated 5 years ago
- ☆12Updated last year
- eyeriss-chisel3☆40Updated 2 years ago
- ☆19Updated last year
- A co-design architecture on sparse attention☆50Updated 3 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆32Updated 5 years ago